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<title>XORPD: Bitwise Logical XOR for Double-Precision Floating-Point Values (x86 Instruction Set Reference)</title>
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<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>XORPD: Bitwise Logical XOR for Double-Precision Floating-Point Values (x86 Instruction Set Reference)</title>
<h1>XORPD</h1>
<h2>Bitwise Logical XOR for Double-Precision Floating-Point Values</h2>
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<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
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<td class="grid"><code>66 0F 57 /r</code></td>
<td class="grid"><code>XORPD xmm1, xmm2/m128</code></td>
<td class="grid">Bitwise exclusive-OR of xmm2/m128 and xmm1..</td>
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<th>Description</th>
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<p>Performs a bitwise logical exclusive-OR of the two packed double-precision floating-point values from the source operand (second operand) and the destination operand (first operand), and stores the result in the destination operand. The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register.</p>
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<pre>Destination<span class="operator">[</span><span class="number">0..127</span><span class="operator">]</span> <span class="operator">=</span> Destination<span class="operator">[</span><span class="number">0..127</span><span class="operator">]</span> <span class="operator">^</span> Source<span class="operator">[</span><span class="number">0..127</span><span class="operator">]</span><span class="operator">;</span>
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<th>Instruction</th>
<th>Latency</th>
<th>Throughput</th>
<th>Execution Unit</th>
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<tr><td class="grid"><code>CPUID</code></td><td class="grid">0F3n/0F2n/069n</td><td class="grid">0F3n/0F2n/069n</td><td class="grid">0F2n</td></tr>
<tr><td class="grid"><code>XORPD xmm, xmm</code></td><td class="grid">4/4/1</td><td class="grid">2/2/1</td><td class="grid">MMX_ALU</td></tr>
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