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<title>ANDPS: Bitwise Logical AND of Packed Single-Precision Floating-Point Values (x86 Instruction Set Reference)</title>
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<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>ANDPS: Bitwise Logical AND of Packed Single-Precision Floating-Point Values (x86 Instruction Set Reference)</title>
<h1>ANDPS</h1>
<h2>Bitwise Logical AND of Packed Single-Precision Floating-Point Values</h2>
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<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
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<td class="grid"><code>0F 54 /r</code></td>
<td class="grid"><code>ANDPS xmm1, xmm2/m128</code></td>
<td class="grid">Bitwise logical AND of xmm2/m128 and xmm1.</td>
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<th>Description</th>
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<p>Performs a bitwise logical AND of the four packed single-precision floating-point values from the source operand (second operand) and the destination operand (first operand), and stores the result in the destination operand. The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register.</p>
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<th>Operation</th>
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<pre>Destination<span class="operator">[</span><span class="number">0..127</span><span class="operator">]</span> <span class="operator">=</span> Destination<span class="operator">[</span><span class="number">0..127</span><span class="operator">]</span> <span class="operator">&</span> Source<span class="operator">[</span><span class="number">0..127</span><span class="operator">]</span><span class="operator">;</span>
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<th>SIMD Floating-Point Exceptions</th>
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None.
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<th>Protected Mode Exceptions</th>
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<tr><td><code>#GP(0)</code></td><td>For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#GP(0)</code></td><td>For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#SS(0)</code></td><td>For an illegal address in the SS segment.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>For a page fault.</td></tr>
<tr><td><code>#NM</code></td><td>If TS in CR0 is set.</td></tr>
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<th>Real-Address Mode Exceptions</th>
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<tr><td><code>#GP(0)</code></td><td>If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH.</td></tr>
<tr><td><code>#NM</code></td><td>If TS in CR0 is set.</td></tr>
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<th>Virtual-8086 Mode Exceptions</th>
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Same exceptions as in Real Address Mode
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<tr><td><code>#PF(fault-code)</code></td><td>For a page fault.</td></tr>
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<th>Instruction</th>
<th>Latency</th>
<th>Throughput</th>
<th>Execution Unit</th>
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<tr><td class="grid"><code>CPUID</code></td><td class="grid">0F3n/0F2n/069n</td><td class="grid">0F3n/0F2n/069n</td><td class="grid">0F2n</td></tr>
<tr><td class="grid"><code>ANDPS xmm, xmm</code></td><td class="grid">4/4/2</td><td class="grid">2/2/2</td><td class="grid">MMX_ALU</td></tr>
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