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<title>ANDNPD: Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values (x86 Instruction Set Reference)</title>
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<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>ANDNPD: Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values (x86 Instruction Set Reference)</title>
<h1>ANDNPD</h1>
<h2>Bitwise Logical AND NOT of Packed Double-Precision Floating-Point Values</h2>
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<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
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<td class="grid"><code>66 0F 55 /r</code></td>
<td class="grid"><code>ANDNPD xmm1, xmm2/m128</code></td>
<td class="grid">Bitwise logical AND NOT of xmm2/m128 and xmm1.</td>
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<th>Description</th>
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<p>Inverts the bits of the two packed double-precision floating-point values in the destination operand (first operand), performs a bitwise logical AND of the two packed double-precision floating-point values in the source operand (second operand) and the temporary inverted result, and stores the result in the destination operand. The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register.</p>
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<th>Operation</th>
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<pre>Destination<span class="operator">[</span><span class="number">0..127</span><span class="operator">]</span> <span class="operator">=</span> <span class="operator">~</span>Destination<span class="operator">[</span><span class="number">0..127</span><span class="operator">]</span> <span class="operator">&</span> Source<span class="operator">[</span><span class="number">0..127</span><span class="operator">]</span><span class="operator">;</span>
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<th>SIMD Floating-Point Exceptions</th>
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None.
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<th>Protected Mode Exceptions</th>
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<tr><td><code>#GP(0)</code></td><td>For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#GP(0)</code></td><td>For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#SS(0)</code></td><td>For an illegal address in the SS segment.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>For a page fault.</td></tr>
<tr><td><code>#NM</code></td><td>If TS in CR0 is set.</td></tr>
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<th>Real-Address Mode Exceptions</th>
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<tr><td><code>#GP(0)</code></td><td>If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH.</td></tr>
<tr><td><code>#NM</code></td><td>If TS in CR0 is set.</td></tr>
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<th>Virtual-8086 Mode Exceptions</th>
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Same exceptions as in Real Address Mode
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<tr><td><code>#PF(fault-code)</code></td><td>For a page fault.</td></tr>
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