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<title>MAXSS: Return Maximum Scalar Single-Precision Floating-Point Value (x86 Instruction Set Reference)</title>
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<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>MAXSS: Return Maximum Scalar Single-Precision Floating-Point Value (x86 Instruction Set Reference)</title>
<h1>MAXSS</h1>
<h2>Return Maximum Scalar Single-Precision Floating-Point Value</h2>
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<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
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<td class="grid"><code>F3 0F 5F /r</code></td>
<td class="grid"><code>MAXSS xmm1, xmm2/m32</code></td>
<td class="grid">Return the maximum scalar single-precision floating-point value between xmm2/mem32 and xmm1.</td>
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<th>Description</th>
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<p>Compares the low single-precision floating-point values in the destination operand (first operand) and the source operand (second operand), and returns the maximum value to the low doubleword of the destination operand. The source operand can be an XMM register or a 32-bit memory location. The destination operand is an XMM register. When the source operand is a memory operand, only 32 bits are accessed. The three high-order doublewords of the destination operand remain unchanged.</p>
<p>If the values being compared are both 0.0s (of either sign), the value in the second operand (source operand) is returned. If a value in the second operand is an SNaN, that SNaN is returned unchanged to the destination (that is, a QNaN version of the SNaN is not returned).</p>
<p>If only one value is a NaN (SNaN or QNaN) for this instruction, the second operand (source operand), either a NaN or a valid floating-point value, is written to the result. If instead of this behavior, it is required that the NaN source operand (from either the first or second operand) be returned, the action of MAXSS can be emulated using a sequence of instructions, such as, a comparison followed by AND, ANDN and OR.</p>
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<pre><span class="keyword">if</span><span class="operator">(</span><span class="operator">(</span>Destination<span class="operator">[</span><span class="number">0..31</span><span class="operator">]</span> <span class="operator">==</span> <span class="number">0.0</span> <span class="operator">&&</span> Source<span class="operator">[</span><span class="number">0..31</span><span class="operator">]</span> <span class="operator">==</span> <span class="number">0.0</span><span class="operator">)</span> <span class="operator">||</span> IsSNaN<span class="operator">(</span>Destination<span class="operator">[</span><span class="number">0..31</span><span class="operator">]</span><span class="operator">)</span> <span class="operator">||</span> IsSNaN<span class="operator">(</span>Source<span class="operator">[</span><span class="number">0..31</span><span class="operator">]</span><span class="operator">)</span> <span class="operator">||</span> Destination<span class="operator">[</span><span class="number">0..31</span><span class="operator">]</span> <span class="operator"><=</span> Source<span class="operator">[</span><span class="number">0..31</span><span class="operator">]</span><span class="operator">)</span> Destination<span class="operator">[</span><span class="number">0..31</span><span class="operator">]</span> <span class="operator">=</span> Source<span class="operator">[</span><span class="number">0..31</span><span class="operator">]</span><span class="operator">;</span>
<span class="comment">//Destination[32..127] is unchanged</span>
</pre>
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<th>SIMD Floating-Point Exceptions</th>
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<tr><td><code>Invalid</code></td><td>(including QNaN source operand), Denormal.</td></tr>
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<th>Protected Mode Exceptions</th>
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<tr><td><code>#GP(0)</code></td><td>For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.</td></tr>
<tr><td><code>#GP(0)</code></td><td>For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>For a page fault.</td></tr>
<tr><td><code>#NM</code></td><td>If TS in CR0 is set.</td></tr>
<tr><td><code>#XM</code></td><td>If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.</td></tr>
<tr><td><code>#UD</code></td><td>If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 0. If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag SSE is 0.</td></tr>
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<th>Real-Address Mode Exceptions</th>
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<tr><td><code>#GP(0)</code></td><td>If any part of the operand lies outside the effective address space from 0 to FFFFH.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If any part of the operand lies outside the effective address space from 0 to FFFFH.</td></tr>
<tr><td><code>#NM</code></td><td>If TS in CR0 is set.</td></tr>
<tr><td><code>#XM</code></td><td>If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.</td></tr>
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<th>Virtual-8086 Mode Exceptions</th>
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Same exceptions as in Real Address Mode
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<tr><td><code>#PF(fault-code)</code></td><td>For a page fault.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>For a page fault.</td></tr>
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<th>Instruction</th>
<th>Latency</th>
<th>Throughput</th>
<th>Execution Unit</th>
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<tr><td class="grid"><code>CPUID</code></td><td class="grid">0F3n/0F2n</td><td class="grid">0F3n/0F2n</td><td class="grid">0F2n</td></tr>
<tr><td class="grid"><code>MAXSS xmm, xmm</code></td><td class="grid">5/4</td><td class="grid">2/2</td><td class="grid">FP_ADD</td></tr>
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