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<title>CVTPI2PS: Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values (x86 Instruction Set Reference)</title>
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<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>CVTPI2PS: Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values (x86 Instruction Set Reference)</title>
<h1>CVTPI2PS</h1>
<h2>Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point Values</h2>
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<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
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<td class="grid"><code>0F 2A /r</code></td>
<td class="grid"><code>CVTPI2PS xmm, mm/m64</code></td>
<td class="grid">Convert two signed doubleword integers from mm/m64 to two single-precision floating-point values in xmm.</td>
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<th>Description</th>
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<p>Converts two packed signed doubleword integers in the source operand (second operand) to two packed single-precision floating-point values in the destination operand (first operand). The source operand can be an MMX technology register or a 64-bit memory location. The destination operand is an XMM register. The results are stored in the low quadword of the destination operand, and the high quadword remains unchanged. When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register.</p>
<p>This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU floating-point exception is pending, the exception is handled before the CVTPI2PS instruction is executed.</p>
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<pre>Destination<span class="operator">[</span><span class="number">0..31</span><span class="operator">]</span> <span class="operator">=</span> ConvertIntegerToFloat<span class="operator">(</span>Source<span class="operator">[</span><span class="number">0..31</span><span class="operator">]</span><span class="operator">)</span><span class="operator">;</span>
Destination<span class="operator">[</span><span class="number">32..63</span><span class="operator">]</span> <span class="operator">=</span> ConvertIntegerToFloat<span class="operator">(</span>Source<span class="operator">[</span><span class="number">32..63</span><span class="operator">]</span><span class="operator">)</span><span class="operator">;</span>
<span class="comment">//high quadword of destination remains unchanged</span>
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<th>SIMD Floating-Point Exceptions</th>
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Precision.
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<th>Protected Mode Exceptions</th>
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<tr><td><code>#GP(0)</code></td><td>For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.</td></tr>
<tr><td><code>#GP(0)</code></td><td>For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.</td></tr>
<tr><td><code>#SS(0)</code></td><td>For an illegal address in the SS segment.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>For a page fault.</td></tr>
<tr><td><code>#NM</code></td><td>If TS in CR0 is set.</td></tr>
<tr><td><code>#MF</code></td><td>If there is a pending x87 FPU exception.</td></tr>
<tr><td><code>#XM</code></td><td>If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.</td></tr>
<tr><td><code>#UD</code></td><td>If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 0. If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag SSE is 0.</td></tr>
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<th>Real-Address Mode Exceptions</th>
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<tr><td><code>GP(0)</code></td><td>If any part of the operand lies outside the effective address space from 0 to FFFFH.</td></tr>
<tr><td><code>GP(0)</code></td><td>If any part of the operand lies outside the effective address space from 0 to FFFFH.</td></tr>
<tr><td><code>#NM</code></td><td>If TS in CR0 is set.</td></tr>
<tr><td><code>#MF</code></td><td>If there is a pending x87 FPU exception.</td></tr>
<tr><td><code>#XM</code></td><td>If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.</td></tr>
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<th>Virtual-8086 Mode Exceptions</th>
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Same exceptions as in Real Address Mode
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<tr><td><code>#PF(fault-code)</code></td><td>For a page fault.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>For a page fault.</td></tr>
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<th>Instruction</th>
<th>Latency</th>
<th>Throughput</th>
<th>Execution Unit</th>
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<tr><td class="grid"><code>CPUID</code></td><td class="grid">0F3n/0F2n/069n</td><td class="grid">0F3n/0F2n/069n</td><td class="grid">0F2n</td></tr>
<tr><td class="grid"><code>CVTPI2PS xmm, mm</code></td><td class="grid">12/11/3</td><td class="grid">2/4/1</td><td class="grid">MMX_ALU FP_ADD MMX_SHFT</td></tr>
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