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<title>CVTSS2SI: Convert Scalar Single-Precision Floating-Point Value to Doubleword Integer (x86 Instruction Set Reference)</title>
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<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>CVTSS2SI: Convert Scalar Single-Precision Floating-Point Value to Doubleword Integer (x86 Instruction Set Reference)</title>
<h1>CVTSS2SI</h1>
<h2>Convert Scalar Single-Precision Floating-Point Value to Doubleword Integer</h2>
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<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
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<td class="grid"><code>F3 0F 2D /r</code></td>
<td class="grid"><code>CVTSS2SI r32, xmm/m32</code></td>
<td class="grid">Convert one single-precision floating-point value from xmm/m32 to one signed doubleword integer in r32.</td>
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<th>Description</th>
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<td class="instruction_set_reference_box">
<p>Converts a single-precision floating-point value in the source operand (second operand) to a signed doubleword integer in the destination operand (first operand). The source operand can be an XMM register or a 32-bit memory location. The destination operand is a general-purpose register. When the source operand is an XMM register, the single-precision floating-point value is contained in the low doubleword of the register.</p>
<p>When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register. If a converted result is larger than the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value (80000000H) is returned.</p>
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<pre>Destination<span class="operator">[</span><span class="number">0..31</span><span class="operator">]</span> <span class="operator">=</span> ConvertFloatToInteger<span class="operator">(</span>Source<span class="operator">[</span><span class="number">0..31</span><span class="operator">]</span><span class="operator">)</span><span class="operator">;</span>
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<th>SIMD Floating-Point Exceptions</th>
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Invalid, Precision.
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<th>Protected Mode Exceptions</th>
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<tr><td><code>#GP(0)</code></td><td>For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.</td></tr>
<tr><td><code>#GP(0)</code></td><td>For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.</td></tr>
<tr><td><code>#SS(0)</code></td><td>For an illegal address in the SS segment.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>For a page fault.</td></tr>
<tr><td><code>#NM</code></td><td>If TS in CR0 is set.</td></tr>
<tr><td><code>#XM</code></td><td>If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.</td></tr>
<tr><td><code>#UD</code></td><td>If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 0. If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag SSE is 0.</td></tr>
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<th>Real-Address Mode Exceptions</th>
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<tr><td><code>#GP(0)</code></td><td>If any part of the operand lies outside the effective address space from 0 to FFFFH.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If any part of the operand lies outside the effective address space from 0 to FFFFH.</td></tr>
<tr><td><code>#NM</code></td><td>If TS in CR0 is set.</td></tr>
<tr><td><code>#XM</code></td><td>If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.</td></tr>
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<th>Virtual-8086 Mode Exceptions</th>
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Same exceptions as in Real Address Mode
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<tr><td><code>#PF(fault-code)</code></td><td>For a page fault.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>For a page fault.</td></tr>
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<th>Instruction</th>
<th>Latency</th>
<th>Throughput</th>
<th>Execution Unit</th>
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<tr><td class="grid"><code>CPUID</code></td><td class="grid">0F3n/0F2n/069n</td><td class="grid">0F3n/0F2n/069n</td><td class="grid">0F2n</td></tr>
<tr><td class="grid"><code>CVTSS2SI r32, xmm</code></td><td class="grid">9/8/4</td><td class="grid">2/2/1</td><td class="grid">FP_ADD FP_MISC</td></tr>
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