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<title>ADC: Add with Carry (x86 Instruction Set Reference)</title>
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<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>ADC: Add with Carry (x86 Instruction Set Reference)</title>
<h1>ADC</h1>
<h2>Add with Carry</h2>
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<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
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<td class="grid"><code>14 ib</code></td>
<td class="grid"><code>ADC AL, imm8</code></td>
<td class="grid">Add with carry imm8 to AL</td>
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<td class="grid"><code>15 iw</code></td>
<td class="grid"><code>ADC AX, imm16</code></td>
<td class="grid">Add with carry imm16 to AX</td>
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<td class="grid"><code>15 id</code></td>
<td class="grid"><code>ADC EAX, imm32</code></td>
<td class="grid">Add with carry imm32 to EAX</td>
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<tr>
<td class="grid"><code>80 /2 ib</code></td>
<td class="grid"><code>ADC r/m8, imm8</code></td>
<td class="grid">Add with carry imm8 to r/m8</td>
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<td class="grid"><code>81 /2 iw</code></td>
<td class="grid"><code>ADC r/m16, imm16</code></td>
<td class="grid">Add with carry imm16 to r/m16</td>
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<tr>
<td class="grid"><code>81 /2 id</code></td>
<td class="grid"><code>ADC r/m32, imm32</code></td>
<td class="grid">Add with CF imm32 to r/m32</td>
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<tr>
<td class="grid"><code>83 /2 ib</code></td>
<td class="grid"><code>ADC r/m16, imm8</code></td>
<td class="grid">Add with CF sign-extended imm8 to r/m16</td>
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<td class="grid"><code>83 /2 ib</code></td>
<td class="grid"><code>ADC r/m32, imm8</code></td>
<td class="grid">Add with CF sign-extended imm8 into r/m32</td>
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<td class="grid"><code>10 /r</code></td>
<td class="grid"><code>ADC r/m8, r8</code></td>
<td class="grid">Add with carry byte register to r/m8</td>
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<td class="grid"><code>11 /r</code></td>
<td class="grid"><code>ADC r/m16, r16</code></td>
<td class="grid">Add with carry r16 to r/m16</td>
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<td class="grid"><code>11 /r</code></td>
<td class="grid"><code>ADC r/m32, r32</code></td>
<td class="grid">Add with CF r32 to r/m32</td>
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<td class="grid"><code>12 /r</code></td>
<td class="grid"><code>ADC r8, r/m8</code></td>
<td class="grid">Add with carry r/m8 to byte register</td>
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<td class="grid"><code>13 /r</code></td>
<td class="grid"><code>ADC r16, r/m16</code></td>
<td class="grid">Add with carry r/m16 to r16</td>
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<tr>
<td class="grid"><code>13 /r</code></td>
<td class="grid"><code>ADC r32, r/m32</code></td>
<td class="grid">Add with CF r/m32 to r32</td>
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<th>Description</th>
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<p>Adds the destination operand (first operand), the source operand (second operand), and the carry (CF) flag and stores the result in the destination operand. The destination operand can be a register or a memory location; the source operand can be an immediate, a register, or a memory location. (However, two memory operands cannot be used in one instruction.) The state of the CF flag represents a carry from a previous addition. When an immediate value is used as an operand, it is sign-extended to the length of the destination operand format.</p>
<p>The ADC instruction does not distinguish between signed or unsigned operands. Instead, the processor evaluates the result for both data types and sets the OF and CF flags to indicate a carry in the signed or unsigned result, respectively. The SF flag indicates the sign of the signed result.</p>
<p>The ADC instruction is usually executed as part of a multibyte or multiword addition in which an ADD instruction is followed by an ADC instruction.</p>
<p>This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.</p>
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<th>Operation</th>
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<td class="instruction_set_reference_box">
<pre>Destination <span class="operator">=</span> Destination <span class="operator">+</span> Source <span class="operator">+</span> CF<span class="operator">;</span>
</pre>
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<th>Flags affected</th>
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<td class="instruction_set_reference_box">
<p>The OF, SF, ZF, AF, CF, and PF flags are set according to the result.
</p>
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<th>Protected Mode Exceptions</th>
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<tr><td><code>#GP(0)</code></td><td>If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
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<th>Real-Address Mode Exceptions</th>
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<td class="instruction_set_reference_box">
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<table class="operations_table">
<tr><td><code>#GP</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#GP</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
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<th>Virtual-8086 Mode Exceptions</th>
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<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
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<th>Instruction</th>
<th>Latency</th>
<th>Throughput</th>
<th>Execution Unit</th>
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<tr><td class="grid"><code>CPUID</code></td><td class="grid">0F3n/0F2n</td><td class="grid">0F3n/0F2n</td><td class="grid">0F2n</td></tr>
<tr><td class="grid"><code>ADC reg, reg</code></td><td class="grid">8/8</td><td class="grid">3/3</td><td class="grid">-</td></tr>
<tr><td class="grid"><code>ADC reg, imm</code></td><td class="grid">8/6</td><td class="grid">2/2</td><td class="grid">ALU</td></tr>
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