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<title>DIVSS: Divide Scalar Single-Precision Floating-Point Values (x86 Instruction Set Reference)</title>
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<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>DIVSS: Divide Scalar Single-Precision Floating-Point Values (x86 Instruction Set Reference)</title>
<h1>DIVSS</h1>
<h2>Divide Scalar Single-Precision Floating-Point Values</h2>
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<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
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<td class="grid"><code>F3 0F 5E /r</code></td>
<td class="grid"><code>DIVSS xmm1, xmm2/m32</code></td>
<td class="grid">Divide low single-precision floating-point value in xmm1 by low single-precision floating-point value in xmm2/m32.</td>
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<th>Description</th>
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<td class="instruction_set_reference_box">
<p>Divides the low single-precision floating-point value in the destination operand (first operand) by the low single-precision floating-point value in the source operand (second operand), and stores the single-precision floating-point result in the destination operand. The source operand can be an XMM register or a 32-bit memory location. The destination operand is an XMM register. The three high-order doublewords of the destination operand remain unchanged. See Figure 10-6 in the IA-32 Intel Architecture Software Developer's Manual, Volume 1 for an illustration of a scalar single-precision floating-point operation.</p>
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<th>Operation</th>
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<pre>Destination<span class="operator">[</span><span class="number">0..31</span><span class="operator">]</span> <span class="operator">=</span> Destination<span class="operator">[</span><span class="number">0..31</span><span class="operator">]</span> / Source<span class="operator">[</span><span class="number">0..31</span><span class="operator">]</span><span class="operator">;</span>
<span class="comment">//Destination[32..127] remains unchanged</span>
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<th>SIMD Floating-Point Exceptions</th>
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<td class="instruction_set_reference_box">
Overflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal.
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<th>Protected Mode Exceptions</th>
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<tr><td><code>#GP(0)</code></td><td>For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.</td></tr>
<tr><td><code>#GP(0)</code></td><td>For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.</td></tr>
<tr><td><code>#SS(0)</code></td><td>For an illegal address in the SS segment.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>For a page fault.</td></tr>
<tr><td><code>#NM</code></td><td>If TS in CR0 is set.</td></tr>
<tr><td><code>#XM</code></td><td>If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.</td></tr>
<tr><td><code>#UD</code></td><td>If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 0. If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag SSE is 0.</td></tr>
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<th>Real-Address Mode Exceptions</th>
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<tr><td><code>#GP(0)</code></td><td>If any part of the operand lies outside the effective address space from 0 to FFFFH.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If any part of the operand lies outside the effective address space from 0 to FFFFH.</td></tr>
<tr><td><code>#NM</code></td><td>If TS in CR0 is set.</td></tr>
<tr><td><code>#XM</code></td><td>If an unmasked SIMD floating-point exception and OSXMMEXCPT in CR4 is 1.</td></tr>
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<th>Virtual-8086 Mode Exceptions</th>
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Same exceptions as in Real Address Mode
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<tr><td><code>#PF(fault-code)</code></td><td>For a page fault.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>For a page fault.</td></tr>
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<th>Instruction</th>
<th>Latency</th>
<th>Throughput</th>
<th>Execution Unit</th>
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<tr><td class="grid"><code>CPUID</code></td><td class="grid">0F3n/0F2n</td><td class="grid">0F3n/0F2n</td><td class="grid">0F2n</td></tr>
<tr><td class="grid"><code>DIVSS xmm, xmm</code></td><td class="grid">32/23</td><td class="grid">32/23</td><td class="grid">FP_DIV</td></tr>
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