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<title>INC: Increment by 1 (x86 Instruction Set Reference)</title>
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<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>INC: Increment by 1 (x86 Instruction Set Reference)</title>
<h1>INC</h1>
<h2>Increment by 1</h2>
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<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
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<td class="grid"><code>FE /0</code></td>
<td class="grid"><code>INC r/m8</code></td>
<td class="grid">Increment r/m byte by 1.</td>
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<tr>
<td class="grid"><code>FF /0</code></td>
<td class="grid"><code>INC r/m16</code></td>
<td class="grid">Increment r/m word by 1.</td>
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<tr>
<td class="grid"><code>FF /0</code></td>
<td class="grid"><code>INC r/m32</code></td>
<td class="grid">Increment r/m doubleword by 1.</td>
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<td class="grid"><code>40+ rw</code></td>
<td class="grid"><code>INC r16</code></td>
<td class="grid">Increment word register by 1.</td>
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<td class="grid"><code>40+ rd</code></td>
<td class="grid"><code>INC r32</code></td>
<td class="grid">Increment doubleword register by 1.</td>
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<th>Description</th>
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<td class="instruction_set_reference_box">
<p>Adds 1 to the destination operand, while preserving the state of the CF flag. The destination operand can be a register or a memory location. This instruction allows a loop counter to be updated without disturbing the CF flag. (Use a ADD instruction with an immediate operand of 1 to perform an increment operation that does updates the CF flag.) This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.</p>
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<th>Operation</th>
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<td class="instruction_set_reference_box">
<pre>Destination <span class="operator">=</span> Destination <span class="operator">+</span> <span class="number">1</span><span class="operator">;</span>
</pre>
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<th>Flags affected</th>
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<td class="instruction_set_reference_box">
<p>The CF flag is not affected. The OF, SF, ZF, AF, and PF flags are set according to the result.
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<th>Protected Mode Exceptions</th>
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<td class="instruction_set_reference_box">
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<tr><td><code>#GP(0)</code></td><td>If the destination operand is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If the destination operand is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
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<th>Real-Address Mode Exceptions</th>
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<td class="instruction_set_reference_box">
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<table class="operations_table">
<tr><td><code>#GP</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#GP</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
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<th>Virtual-8086 Mode Exceptions</th>
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<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
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<th>Instruction</th>
<th>Latency</th>
<th>Throughput</th>
<th>Execution Unit</th>
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<tr><td class="grid"><code>CPUID</code></td><td class="grid">0F3n/0F2n</td><td class="grid">0F3n/0F2n</td><td class="grid">0F2n</td></tr>
<tr><td class="grid"><code>INC</code></td><td class="grid">1/1</td><td class="grid">0.5/0.5</td><td class="grid">ALU</td></tr>
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