Kestrel-3

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121 check-ins tagged with "trunk"

2019-07-15
04:47
[a783307bfd] Leaf: WIP: Implement A-channel of TileLink interface. DOES NOT YET DEAL WITH UNALIGNED ADDRESSES; instead, just ignores low-order address bits depending on size of datum being written. (user: kc5tja tags: trunk)
2019-06-06
07:41
[daf647810c] update psp (user: kc5tja tags: trunk)
07:39
[7170d9c66c] Complete trunk register file source indices logic. (user: kc5tja tags: trunk)
07:19
[c387b96556] Add SUM_REQ, but I renamed it to CU_READ_VALUES. When asserted, it tells the CU when to capture the values of the register file on the trunk's register data ports. (user: kc5tja tags: trunk)
03:13
[2e36a268b3] When GO_READ is asserted by the picker, drop out of read state. (user: kc5tja tags: trunk)
2019-06-04
15:40
[87d90f5c93] WIP: FU logic recognizes when function units broadcast results on the trunk. Keeps track of operand available status. Drives READ_REQ signal when the FU feels all operands are now ready. (user: kc5tja tags: trunk)
2019-06-02
22:38
[2d67e26722] initial import for FU logic (user: kc5tja tags: trunk)
22:34
[e3c8c82fe7] Relabel some of the CU signals for easier recall of who drives them (user: kc5tja tags: trunk)
06:12
[3425f3c9f4] psp update (user: kc5tja tags: trunk)
05:28
[0c5c321cf6] WIP! This completes the add/subtract logic for the add/store computation unit. The precise needs of the "store" logic will be dictated by how the state machine in the function unit is implemented, so I'll cross that bridge when I get there. (user: kc5tja tags: trunk)
03:16
[46868584f7] WIP: First CDC 6600-inspired add/store computation unit. Experimental (user: kc5tja tags: trunk)
2019-05-28
01:00
[d7b385618d] Pass I port D channel error signal through to IXU for synchronous trap processing (user: kc5tja tags: trunk)
00:44
[d23d900a8b] Remember to double-check the lowest 2 address bits (user: kc5tja tags: trunk)
00:40
[f37147ffb1] Relabel interfaces properly; expose iq_flush (user: kc5tja tags: trunk)
00:27
[16b97e0e8b] Jump request and ack interface (user: kc5tja tags: trunk)
2019-05-27
22:53
[2dbe6f9e6d] Implement o_iq_valid handshake signal. Note that it is pulsed!! (See comments in code for more details.) (user: kc5tja tags: trunk)
2019-05-26
01:37
[23a3a9c2af] iq_address and iq_inst_addr implemented. Confirmed proper word routing from the fetched dword. I need to double-check proper handshaking next (e.g., iq_ready and iq_valid), and after that is done, work on the control flow functionality. (user: kc5tja tags: trunk)
2019-05-06
01:41
[e91ccded29] Finished IFU A-channel for instruction fetch port (TileLink). (user: kc5tja tags: trunk)
2019-05-05
07:51
[e17b606295] Makefile update to remove old ilang files (user: kc5tja tags: trunk)
07:50
[33a2716e57] Support the byte lane select mask (user: kc5tja tags: trunk)
07:34
[5c7b25760b] update psp (user: kc5tja tags: trunk)
07:20
[af1995818c] B/c the fetch_counter was treated as an anonymous input port to the module, allowing sby to tweak its value. Very unintuitive!! (user: kc5tja tags: trunk)
07:17
[3a96327a8f] WIP: Why u no work? Fails induction for unknown reasons (user: kc5tja tags: trunk)
03:57
[866dcdadac] update psp (user: kc5tja tags: trunk)
03:56
[3018838aa9] Initial IFU code (user: kc5tja tags: trunk)
2019-05-04
15:54
[9f51a63046] PSP update and spec update (user: kc5tja tags: trunk)
2019-05-02
22:34
[51b29796b7] Consolidate tests into per-module tests (user: kc5tja tags: trunk)
22:03
[13a75afbcd] Use nmigen version of tools.py (more maintainable) (user: kc5tja tags: trunk)
21:53
[c8c8464c5e] Migrate tests for UpCounterCSR to nmigen (user: kc5tja tags: trunk)
18:30
[c09510ecfd] Migrate MemCSR tests to nmigen (user: kc5tja tags: trunk)
17:52
[d38e951c0e] Augment clean target to account for nmigen's spec_xxx directories (user: kc5tja tags: trunk)
17:50
[09291e359f] Migrate InputCSR tests to nmigen (user: kc5tja tags: trunk)
17:30
[c216582c93] Migrate tests for ConstantCSR to nmigen (user: kc5tja tags: trunk)
05:23
[138c5505a1] Remove dead code (user: kc5tja tags: trunk)
05:22
[0e9f6538b4] Convert formal testbench to nmigen for CSRSelect (user: kc5tja tags: trunk)
04:55
[a5b58db554] Remove Verilog-based formal test bench for MStatus (user: kc5tja tags: trunk)
04:44
[00a555b8ef] Remove from nmigen import * in favor of explicit imports (user: kc5tja tags: trunk)
03:21
[c2e3819404] Thank you Luke Kenneth Casson Leighton for this contribution. This shows me both where I went wrong in my previous attempts to apply nmigen towards formal verification, but also a better interface to make formal tests run automatically than through a stack of mostly-but-not-exactly-identical Makefile rules. I will start evolving the codebase to use this new approach. (user: kc5tja tags: trunk)
2019-04-29
06:52
[d1cdbff14a] Updating spec and PSP (user: kc5tja tags: trunk)
2019-04-09
05:23
[6c559135a3] Add (M)CYCLE, (M)INSTRET (user: kc5tja tags: trunk)
01:16
[615dbc6e78] Implement MIP register (user: kc5tja tags: trunk)
2019-04-08
07:19
[e67e2d5951] Complete CSRU. No I/Os to outside world yet, though, but those can be added later. From CPU's POV, all CSRs are implemented and properly handle WLRL fields. (user: kc5tja tags: trunk)
00:30
[fcac6fca38] Remove commented old code. (user: kc5tja tags: trunk)
00:29
[6074d7325c] Convert MSTATUS and MIE to use MemCSR (user: kc5tja tags: trunk)
2019-04-07
22:57
[c0dba178f7] Generalize memory-only type CSRs. Some CSRs which have non-memory semantics can, in fact, use MemCSRs as a submodule, and just wrap CSR-specific logic around this. (user: kc5tja tags: trunk)
2019-03-25
08:15
[1629179d84] Begin proving mstatus (user: kc5tja tags: trunk)
06:09
[f311559092] Formally verify InputCSR (user: kc5tja tags: trunk)
05:17
[6facb8fbe2] Formally verify ConstantCSR (user: kc5tja tags: trunk)
04:32
[d460e67f4a] tighten CSRSelect properties (user: kc5tja tags: trunk)
04:24
[f96c5158b4] Formally prove CSRSelect (user: kc5tja tags: trunk)
2019-03-24
19:56
[aa1efe0a7d] Data output logic. (user: kc5tja tags: trunk)
2019-03-23
18:45
[f226214414] Implement MSTATUS. (user: kc5tja tags: trunk)
17:37
[e96a1d61c9] Bringing repo up to date, as I'm giving a demo at SVFIG. (user: kc5tja tags: trunk)
2019-03-18
08:25
[4c2460e8d1] Begin implementation of the CSR Unit. Holy heck, using nMigen for this was totally the right choice. The CSRU module is **tiny** compared to its equivalent Verilog. (user: kc5tja tags: trunk)
2019-03-16
02:45
[2dc9dd15f4] Spec and project data updates. (user: kc5tja tags: trunk)
2019-03-13
07:11
[04d68e52a6] Beginning specification work for the KCP53000B processor design. (user: kc5tja tags: trunk)
2018-11-26
18:16
[3989d347ab] SIA IS PROVEN! The core worked fine. The problem was a bug in my ROMA core instantiation. Celebration time!! (user: kc5tja tags: trunk)
07:36
[f70ab01418] Prove in hardware that the SIA core works. IT DOES. However, there is a bug when sending bytes with relatively few bits set on the low end of the byte (e.g., 0x05 becomes 0x0A on the receiver, while 0x51 remains 0x51 on the receiver). I genuinely have no idea how or why this is happening at this time. (user: kc5tja tags: trunk)
07:35
[315211fe32] Parameterize the SIA core. (user: kc5tja tags: trunk)
05:53
[8d2bf519df] Fucking reset circuitry gets me every time! (user: kc5tja tags: trunk)
01:34
[b06cdcafc5] First cut at a hardware integration test for the SIA (user: kc5tja tags: trunk)
2018-11-25
02:29
[5511953cec] Forgot to remove debugging change to default loopback settings (user: kc5tja tags: trunk)
02:03
[2867a12bc1] Integration test: SIA local loopback test passes! (user: kc5tja tags: trunk)
02:03
[8fe7daff6e] Bug fix: Draw the loopback control bits from the proper data lines. (user: kc5tja tags: trunk)
02:01
[f047e61a8d] Bug fix: make sure loopback control bits are accounted for in formal assertions. (user: kc5tja tags: trunk)
2018-11-01
17:58
[1dd9f6b5cf] WIP: Renovate sia_tilelink.v and properties.vf to work better with Verilator. HOWEVER, Verilator now cannot locate "verilated.h" for some reason. Even if I manually include its path as a -I parameter to gcc, it refuses to find it. NOTE: I'll need to apply these kinds of renovations to all the other Verilog sources in the SIA core, and quite possibly throughout the Kestrel-3 repository as well. UUGH! I hate Verilog so much after this. The Verilog spec is total garbage if nobody is going to bother to follow it. Many thanks to ZipCPU (Dan G.) for isolating what could be one of the biggest bugs of the Kestrel-3, and a major source of what's driving me crazy with this project. (user: kc5tja tags: trunk)
2018-10-31
05:59
[c72d29e3e8] Revise TB to match structure used by ZipCPU (user: kc5tja tags: trunk)
2018-10-30
17:33
[ef48c3f143] Remove uncompilable code (user: kc5tja tags: trunk)
17:14
[857710bfcf] WIP: SIA: Passes induction but not unit tests?! WTF?! I'm getting too old for this crap. (user: kc5tja tags: trunk)
2018-10-26
18:47
[74a8631b27] SIA: Adjust working paths (user: kc5tja tags: trunk)
18:40
[3d2b8fb5b2] Remove unnecessary subdirectories (user: kc5tja tags: trunk)
18:39
[9605232766] WIP: SIA: Clean up directory structure (user: kc5tja tags: trunk)
18:17
[eda0bdb81a] WIP: SIA: First unit test for SIA (user: kc5tja tags: trunk)
16:22
[caf59227ca] WIP: SIA: Top-level (user: kc5tja tags: trunk)
06:51
[ea401e4d06] SIA: Transmit engine seems to be complete. Next step: top-level. Again. (user: kc5tja tags: trunk)
06:24
[d1e65629f7] WIP: SIA: Integrate transmit engine baud rate generator. Having the BRG as a separate module made the top-level unnecessarily complex, as some signal wires were just not used, and others just not needed. Does not yet pass formal. (user: kc5tja tags: trunk)
2018-10-22
02:18
[40bc0dad6e] SIA: Why didn't the merge include the makefile? (user: kc5tja tags: trunk)
02:09
[f6bd84d868] Import roma core from formal branch (user: kc5tja tags: trunk)
02:03
[16aceea475] Merging did the wrong thing with the DMAC. Bring in the latest DMAC. (user: kc5tja tags: trunk)
01:57
[af53196bd7] Formal verification has proven itself as a viable development method. Merging into trunk. (user: kc5tja tags: trunk)
2018-08-29
00:59
[e19f2d7e5c] Attempt to add ROMA verification properties on my own (user: kc5tja tags: trunk)
2018-08-28
21:51
[3ded29d7df] Fixed the clock leak on ROMA core after adding FV to DMAC. Next step: figure out why only one bus transaction is taking place. (user: kc5tja tags: trunk)
21:51
[7756138d89] Fixed the clock leak on ROMA core after adding FV to DMAC. Next step: figure out why only one bus transaction is taking place. (user: kc5tja tags: trunk)
05:55
[0f3c9ade6a] Remove spurious Or operator (user: kc5tja tags: trunk)
05:42
[f2a9d73ac1] Make unit test pass for DMAC (user: kc5tja tags: trunk)
04:40
[eaace617c1] Fix commentary (user: kc5tja tags: trunk)
04:36
[db46c3c0e7] Introduce some formal verification for the DMAC (user: kc5tja tags: trunk)
01:19
[2795fa984f] ROMA + DMAC = working now, due to DDR clock buffer. (user: kc5tja tags: trunk)
2018-08-25
02:34
[1d81dbc235] ROMA: Fix data alignment bug. (user: kc5tja tags: trunk)
00:20
[a79aca60ee] Fix integration test MOSI/MISO assignment (user: kc5tja tags: trunk)
2018-08-24
05:33
[ed4beeb135] WIP: FPGA programs OK; flash programs OK; DMAC seems to be working OK; ROMA seems to be working OK; however, data read back is always $FF on the LEDs. This suggests either the CPLD is interfering with my communications somehow, OR, I'm botching the SPI protocol somehow. Unsure which yet. More research is needed. (user: kc5tja tags: trunk)
00:59
[3444a010e1] Refactor common definitions into shared headers (user: kc5tja tags: trunk)
2018-08-23
23:51
[d3867aab51] ROMA: Support back-to-back transactions (user: kc5tja tags: trunk)
23:29
[f7064f5df0] ROMA: Forgot to drive the CLK output (user: kc5tja tags: trunk)
23:25
[2bccfe58ef] ROMA: I think it is finished. (user: kc5tja tags: trunk)
23:10
[85e9538b39] Confirm proper data output (user: kc5tja tags: trunk)
22:48
[1181e5b5d7] ROMA: Proper D-channel handoff (user: kc5tja tags: trunk)
22:43
[e4574d60c9] Negate SPI Flash CS after 64 data bits read (user: kc5tja tags: trunk)
07:36
[a777854d78] ROMA: Send 21-bit dword-aligned address too (user: kc5tja tags: trunk)
07:20
[cffa191f94] ROMA: Send command byte on read request (user: kc5tja tags: trunk)
07:00
[0892ceaf82] ROMA: Recognize read request (user: kc5tja tags: trunk)
06:02
[768fc08020] ROMA: Slave A-channel first commit (user: kc5tja tags: trunk)
05:48
[e4318b055e] First commit for ROMA core. (user: kc5tja tags: trunk)
2018-08-17
19:47
[c47448ac7d] WIP: Trying to get E2 to build in new environment (user: kc5tja tags: trunk)
17:44
[fe4ca6880a] DXForth source tree (user: kc5tja tags: trunk)
17:39
[711ad764bd] DXForth binary generation (user: kc5tja tags: trunk)
17:38
[f76a09e9d5] Include path support for more sophisticated software builds. (user: kc5tja tags: trunk)
16:54
[97be6cffb8] forgot config (user: kc5tja tags: trunk)
16:53
[f49f4a6b5c] Assembler! (user: kc5tja tags: trunk)
2018-06-09
07:59
[8885fc2223] Properly route data based on fetched address (user: kc5tja tags: trunk)
07:49
[f107429cc3] Update byte enable mask bits (user: kc5tja tags: trunk)
07:36
[841b6fd764] Auto-increment fetch address (user: kc5tja tags: trunk)
06:11
[9ab58d4df7] Support single-cycle execution opportunity. (user: kc5tja tags: trunk)
05:20
[8bb4608b65] Very first TileLink exchange (fixed address, fixed size, fixed alignment). Not too difficult so far. (user: kc5tja tags: trunk)
2018-06-08
06:14
[beaa6900f1] WIP: DMAC: First assertion (user: kc5tja tags: trunk)
05:39
[94011ac807] Forgot the README.md (user: kc5tja tags: trunk)
05:36
[3ba509ef3b] WIP: beginning to work on first core for Kestrel-3. Still learning how to use Verilator properly for TDD purposes. (user: kc5tja tags: trunk)
2018-06-05
06:10
[ddfba64273] Mothballing the Chisel sources, as we'll be working with plain Verilog. It's going to suck. However, it has reduced dependencies, easier installation of build tools, and wider audience of potential contributors. (user: kc5tja tags: trunk)
2017-12-16
07:39
[75ab442d95] Import GPIA-2 core. (user: kc5tja tags: trunk)
06:28
[024b520c4d] Create Chisel template to hold Kestrel-3 cores. (user: kc5tja tags: trunk)
02:26
[3aded20100] initial empty check-in (user: kc5tja tags: trunk)