Kestrel-3

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200 most recent check-ins tagged with "trunk"

2020-02-02
05:30
[3a47f2f9d6] Leaf: Introduce the (:remove ...) directive (user: kc5tja tags: trunk)
01:58
[33dcc7213e] Introduce (:delete ...) command to Brickie. (user: kc5tja tags: trunk)
2020-01-26
18:49
[a28155cb66] Introduce doc and code directives to make "weaving" easier. (user: kc5tja tags: trunk)
16:25
[515b6aefb4] Place definition of lines in appropriate context (user: kc5tja tags: trunk)
2020-01-16
20:10
[63fa3ba241] Introducing Brickie, a literate programming tool written for GForth, but it should be portable to DX-Forth with modest effort. It is based on Akkartik's "tangle" tool, and has similar syntax for markup. Brickie is optimized for my project's needs, however, and will evolve independently of Akkartik's work. Long story short, you write software as layers of related functionality: in a sense, you explicitly name and compose patches which ultimately leads to the finished product. This allows for code and commentary to co-reside, even when chunks of related functionality are widely separated in the source code. See http://akkartik.name/post/wart-layers for more behind the theory of this approach to literate programming. (user: kc5tja tags: trunk)
2020-01-11
04:56
[02c01ec8d4] forgot about m4 (user: kc5tja tags: trunk)
04:50
[77617ea1f5] fix formatting (user: kc5tja tags: trunk)
04:42
[b205b9737b] Contribute official E3 user documentation (user: kc5tja tags: trunk)
03:54
[0154dbff6a] Try to fix build bug on Ubuntu 19.04 cloud box. (This might go on for a while...) (user: kc5tja tags: trunk)
2020-01-09
06:11
[7b40e899bd] Feature parity with E2, but much easier to add new virtual hardware. Also, much easier to support interrupts in the future as well. (user: kc5tja tags: trunk)
2020-01-02
23:59
[8571b9ca73] Restore trunk back to pre-repkg state. (user: kc5tja tags: trunk)
23:45
[db7a0e50d6] Remove vestiges of NRMF. (user: kc5tja tags: trunk)
23:42
[1da36e75d2] Replace NRMF with another non-recursive make system, purpose built. (user: kc5tja tags: trunk)
05:07
[d7b42491d9] Remove config.od; no longer needed. (user: kc5tja tags: trunk)
03:28
[456f3f082f] e3 builds, processes some basic arguments. Need to work on CPU and SIA emulation next. (user: kc5tja tags: trunk)
00:50
[2d4b6522a0] Initial import of initial main.c of initial code for E3. (user: kc5tja tags: trunk)
2020-01-01
03:00
[efcd68a84e] Divorce DX-Forth from processor card-specific ROM image (user: kc5tja tags: trunk)
03:00
[5551f78da0] Oops, I forgot to link Kestrel ROM access into the address decode logic of the emulator. (user: kc5tja tags: trunk)
02:22
[2db30aba6b] Rename rom.asm to cpurom.asm, and clean up compiler warnings (user: kc5tja tags: trunk)
02:05
[62f70e562e] Move origin to $40000 to prep for icoBoard Gamma FPGA bitstream (user: kc5tja tags: trunk)
01:51
[df7de75d56] ...by which I mean split apart the CPU-card functionality from the Kestrel ROM image contents. (user: kc5tja tags: trunk)
01:50
[e1402a7070] Emulator E2 now conforms fully to E3 memory map semantics. Just need to update the DX-Forth image to exploit this. (user: kc5tja tags: trunk)
01:40
[2433110035] Rename unified ROM to the "CPU ROM", the ROM which is intended to reside on the active processor card. Right now, this ROM behaves exactly as it did in the E2 emulator. However, eventually, this ROM will hold the processor's machine-mode bootstrap code and software shims for missing hardware features. (user: kc5tja tags: trunk)
2019-12-31
22:56
[f1c79c7f80] Upgrade to DX-Forth 1.2, which now supports the Kestrel-3/E3 memory map standards (even though the emulator doesn't quite get the firmware address decoding right yet). Fixes a number of signed vs. unsigned bugs found within DX-Forth 1.1, thanks to RAM addresses now being located in negative address space (on 32-bit machines). KNOWN BUG IN DX-FORTH 1.2: there is no way to enter an unsigned 32-bit number or unsigned 16-bit number in source form. So, HEX C000000 or HEX C000 will result in negative numbers. (This bug also existed in DX-Forth 1.1, but I wasn't aware of it.) This is an artifact of LITERAL attempting to save space in the dictionary by using the most compact numeric representation. Three workarounds exist: (1) create a parsing word which parses the next number and manually compiles a 64-bit number; (2) Wait for DX-Forth 1.3 to roll out some kind of fix for this issue; OR, (3) follow such numbers (perhaps computed from elsewhere) with explicit masks, like -65536 AND, etc. Of course, the third option is to replace DX-Forth 1.x with DX-Forth 2.x and go with native-code compilation, but this will take much longer to get working. (user: kc5tja tags: trunk)
2019-12-30
17:34
[da0ce0827c] Switch from old Redo-based builds back to using GNU Make (specifically using my NRMF package). (user: kc5tja tags: trunk)
2019-12-27
19:27
[9f4e4c255d] Integrated the `a` assembler into the NRMF configuration. (user: kc5tja tags: trunk)
17:37
[803c2a6dc9] Import NRMF files from Github repo (user: kc5tja tags: trunk)
2019-12-26
23:07
[11b423ba53] restoring order now? (user: kc5tja tags: trunk)
22:56
[8182ca29ca] More testing (user: kc5tja tags: trunk)
22:52
[8c2b8498c9] testing, please disregard (user: kc5tja tags: trunk)
2019-12-21
16:36
[aafe97f23b] Testing new install of fossil to see if this will preserve user credentials. (user: kc5tja tags: trunk)
2019-11-12
05:30
[5b58b60f8a] Bringing REPORT up to date. Still not complete, but not entirely happy with the complexity of the firmware design either. I reserve the right to scale things way down in the next version. We shall see where this leads. (user: kc5tja tags: trunk)
2019-10-27
00:52
[cb2c29bfa3] Re-read doc; identified one code section and one whole sub-section which needs updating to the latest I/O channel model. (user: kc5tja tags: trunk)
2019-09-15
23:57
[c6e384b2d2] Refined some more SSP procedures. But, I am finding that complexity is growing beyond my ability to keep it in my head, and am running into limitations when it comes to distinguishing commands intended for the controller or for the units. (user: kc5tja tags: trunk)
06:24
[a6c0c403cb] refining some of the storage protocol requirements before my laptop loses power (user: kc5tja tags: trunk)
2019-09-11
03:25
[46379ac38b] Simplify forth auto-load block logic (user: kc5tja tags: trunk)
2019-09-10
05:48
[bfb02a2af0] I think I have completed the refinement of the boot menu logic. I feel confident I can proceed with the boot source discovery. (user: kc5tja tags: trunk)
04:30
[01899c8062] Switch methods of tracking which steps need refinement. This seems to be an easier approach, and I can track progress in an automated manner with clever use of grep. (user: kc5tja tags: trunk)
2019-09-09
05:06
[985c171204] More refinements; done for this evening though. (user: kc5tja tags: trunk)
04:35
[a903a4c39f] More stepwise refinements to flesh out more boot loader behavioral details, menu item structure, etc. (user: kc5tja tags: trunk)
00:34
[2c2434a794] Missing word radically alters intended meaning of a sentence. (user: kc5tja tags: trunk)
2019-09-08
23:48
[e485309137] Bring in the project report org-mode document. Tracks stepwise refinement of system firmware, hardware design choices, etc. (user: kc5tja tags: trunk)
2019-09-05
03:41
[447c21378e] .skip and .zero support (user: kc5tja tags: trunk)
03:10
[f23325b630] Support .asciz and fix unit test breakage in scanner (user: kc5tja tags: trunk)
02:51
[29d317a6a2] .ascii support (user: kc5tja tags: trunk)
2019-09-03
04:41
[8a46823df5] .8byte, .4byte, and .2byte implemented (user: kc5tja tags: trunk)
04:31
[4f12102c36] .half and .byte supported (user: kc5tja tags: trunk)
04:23
[c0b13ae1bb] Support .word (user: kc5tja tags: trunk)
02:12
[233d4785af] Remove debugging code (user: kc5tja tags: trunk)
02:07
[88de4ec636] String expression support (user: kc5tja tags: trunk)
01:29
[0dda2d09e7] Basic .dword primitive (user: kc5tja tags: trunk)
2019-09-02
23:11
[9688a01a13] First parser integration test (user: kc5tja tags: trunk)
22:27
[82629340d1] Relocate tokens beyond ASCII/UTF-8 boundaries (user: kc5tja tags: trunk)
22:25
[09e88c1248] Unrecognized punctuation are their own symbols. (user: kc5tja tags: trunk)
18:24
[f01e8709f2] Dead code removal (user: kc5tja tags: trunk)
18:19
[ab025af620] tests for octal numbers (user: kc5tja tags: trunk)
18:15
[590014a9f8] support binary constants as well (user: kc5tja tags: trunk)
17:59
[feb73894e7] Numeric constants (unsigned only; parser needed for signed constants) (user: kc5tja tags: trunk)
16:41
[0c54627c0d] Remove dead code from manifest (user: kc5tja tags: trunk)
16:40
[824187d941] Remove dead code from manifest (user: kc5tja tags: trunk)
16:35
[e2b6e66be3] keyword check (naive implementation) (user: kc5tja tags: trunk)
06:18
[e28f0d9a4e] Track line numbers (user: kc5tja tags: trunk)
05:54
[1b3c87c3b9] Scanner grabs identifiers (user: kc5tja tags: trunk)
04:13
[d3ab39fb86] Removing parser again; switching to Wirth-style recursive descent implementation (user: kc5tja tags: trunk)
04:12
[fcf8bd4e65] First scanner tests (user: kc5tja tags: trunk)
2019-08-26
06:49
[6c6a725a22] Introduce failing parser test. Tried shunting yard; does not work for my needs. Must revert to recursive descent with Wirth emission. (user: kc5tja tags: trunk)
2019-08-25
23:17
[651073af86] Forgot to include buffer migration check (user: kc5tja tags: trunk)
23:08
[0449beaa7a] Make sure vector contents is preserved after expansion (user: kc5tja tags: trunk)
22:55
[a52343650b] Dynamic vectors completed (user: kc5tja tags: trunk)
19:16
[af4b7000f7] Start on dynamic vector type. Major refactoring into smaller modules. Inconvenience from lack of shared libraries is showing. (user: kc5tja tags: trunk)
2019-08-24
21:28
[de3957748f] forgot runtests (user: kc5tja tags: trunk)
21:27
[de174e1877] Remove parser; started on wrong foot. Starting over (user: kc5tja tags: trunk)
2019-08-23
06:54
[0be7136182] Try to refactor test engine into a separate module; however, it does not work nearly as well as I would like. (user: kc5tja tags: trunk)
2019-08-21
22:27
[ffc86e1698] prepare to work on parser next (user: kc5tja tags: trunk)
2019-08-17
00:07
[5594d490f9] Finished (for now at least) the section abstraction. (user: kc5tja tags: trunk)
2019-08-16
21:38
[0482ee37fa] WIP: you can emit bytes..dwords into a section now (user: kc5tja tags: trunk)
06:59
[431ffa1b72] Start work on a next-generation assembler for the Tripos/KOS environment. Uses official RISC-V assembly language directives as much as it makes sense to. Not intended to replace gas; but I need something usable in a BCPL and Tripos environment, and gas won't be useful until it either supports hunk format executables or runs under Tripos. (user: kc5tja tags: trunk)
2019-08-05
07:53
[797fafc3c9] Bug fix: branch displacement was missing a bit (user: kc5tja tags: trunk)
06:31
[0708c27675] writeback logic first pass implemented. (user: kc5tja tags: trunk)
03:44
[b705e135a7] SRLI and SRAI -- this completes OP-IMM (user: kc5tja tags: trunk)
03:23
[83070c8d95] AND, OR, XOR (user: kc5tja tags: trunk)
03:21
[26f3c58373] Bug fix for SLTI: -4 < 4 would fail test (user: kc5tja tags: trunk)
03:02
[fe12c3b40e] SLTI and SLTUI (user: kc5tja tags: trunk)
02:49
[d265210c64] SLLI implemented in the IXU (user: kc5tja tags: trunk)
02:30
[b0c8e8b48a] ANDI instruction works. (user: kc5tja tags: trunk)
01:20
[3d81d8061e] Initial integration of ALU into IXU; no tests yet (user: kc5tja tags: trunk)
00:11
[84a26d5484] Simplify the ALU code significantly (user: kc5tja tags: trunk)
2019-08-04
21:41
[9357ad3b2f] Introduce (untested) ALU module, clone of KCP53000 ALU (user: kc5tja tags: trunk)
19:38
[313bd82cd1] capture_operands implemented (user: kc5tja tags: trunk)
07:49
[d9bfda7c63] Preparing to switch everything over to Wishbone B4 Pipelined. (user: kc5tja tags: trunk)
07:48
[2556401d8a] New IXU design, going back to my original ideas of how to build the thing. (user: kc5tja tags: trunk)
2019-07-16
05:45
[8568cc35ae] clarify comment (user: kc5tja tags: trunk)
05:18
[561d833304] WIP: Implement misaligned address detection, and prevent misaligned writes from generating Tilelink transactions. It's up to the FU to terminate the instruction by committing a trap to the trunk bus in a subsequent cycle. (user: kc5tja tags: trunk)
2019-07-15
04:47
[a783307bfd] WIP: Implement A-channel of TileLink interface. DOES NOT YET DEAL WITH UNALIGNED ADDRESSES; instead, just ignores low-order address bits depending on size of datum being written. (user: kc5tja tags: trunk)
2019-06-06
07:41
[daf647810c] update psp (user: kc5tja tags: trunk)
07:39
[7170d9c66c] Complete trunk register file source indices logic. (user: kc5tja tags: trunk)
07:19
[c387b96556] Add SUM_REQ, but I renamed it to CU_READ_VALUES. When asserted, it tells the CU when to capture the values of the register file on the trunk's register data ports. (user: kc5tja tags: trunk)
03:13
[2e36a268b3] When GO_READ is asserted by the picker, drop out of read state. (user: kc5tja tags: trunk)
2019-06-04
15:40
[87d90f5c93] WIP: FU logic recognizes when function units broadcast results on the trunk. Keeps track of operand available status. Drives READ_REQ signal when the FU feels all operands are now ready. (user: kc5tja tags: trunk)
2019-06-02
22:38
[2d67e26722] initial import for FU logic (user: kc5tja tags: trunk)
22:34
[e3c8c82fe7] Relabel some of the CU signals for easier recall of who drives them (user: kc5tja tags: trunk)
06:12
[3425f3c9f4] psp update (user: kc5tja tags: trunk)
05:28
[0c5c321cf6] WIP! This completes the add/subtract logic for the add/store computation unit. The precise needs of the "store" logic will be dictated by how the state machine in the function unit is implemented, so I'll cross that bridge when I get there. (user: kc5tja tags: trunk)
03:16
[46868584f7] WIP: First CDC 6600-inspired add/store computation unit. Experimental (user: kc5tja tags: trunk)
2019-05-28
01:00
[d7b385618d] Pass I port D channel error signal through to IXU for synchronous trap processing (user: kc5tja tags: trunk)
00:44
[d23d900a8b] Remember to double-check the lowest 2 address bits (user: kc5tja tags: trunk)
00:40
[f37147ffb1] Relabel interfaces properly; expose iq_flush (user: kc5tja tags: trunk)
00:27
[16b97e0e8b] Jump request and ack interface (user: kc5tja tags: trunk)
2019-05-27
22:53
[2dbe6f9e6d] Implement o_iq_valid handshake signal. Note that it is pulsed!! (See comments in code for more details.) (user: kc5tja tags: trunk)
2019-05-26
01:37
[23a3a9c2af] iq_address and iq_inst_addr implemented. Confirmed proper word routing from the fetched dword. I need to double-check proper handshaking next (e.g., iq_ready and iq_valid), and after that is done, work on the control flow functionality. (user: kc5tja tags: trunk)
2019-05-06
01:41
[e91ccded29] Finished IFU A-channel for instruction fetch port (TileLink). (user: kc5tja tags: trunk)
2019-05-05
07:51
[e17b606295] Makefile update to remove old ilang files (user: kc5tja tags: trunk)
07:50
[33a2716e57] Support the byte lane select mask (user: kc5tja tags: trunk)
07:34
[5c7b25760b] update psp (user: kc5tja tags: trunk)
07:20
[af1995818c] B/c the fetch_counter was treated as an anonymous input port to the module, allowing sby to tweak its value. Very unintuitive!! (user: kc5tja tags: trunk)
07:17
[3a96327a8f] WIP: Why u no work? Fails induction for unknown reasons (user: kc5tja tags: trunk)
03:57
[866dcdadac] update psp (user: kc5tja tags: trunk)
03:56
[3018838aa9] Initial IFU code (user: kc5tja tags: trunk)
2019-05-04
15:54
[9f51a63046] PSP update and spec update (user: kc5tja tags: trunk)
2019-05-02
22:34
[51b29796b7] Consolidate tests into per-module tests (user: kc5tja tags: trunk)
22:03
[13a75afbcd] Use nmigen version of tools.py (more maintainable) (user: kc5tja tags: trunk)
21:53
[c8c8464c5e] Migrate tests for UpCounterCSR to nmigen (user: kc5tja tags: trunk)
18:30
[c09510ecfd] Migrate MemCSR tests to nmigen (user: kc5tja tags: trunk)
17:52
[d38e951c0e] Augment clean target to account for nmigen's spec_xxx directories (user: kc5tja tags: trunk)
17:50
[09291e359f] Migrate InputCSR tests to nmigen (user: kc5tja tags: trunk)
17:30
[c216582c93] Migrate tests for ConstantCSR to nmigen (user: kc5tja tags: trunk)
05:23
[138c5505a1] Remove dead code (user: kc5tja tags: trunk)
05:22
[0e9f6538b4] Convert formal testbench to nmigen for CSRSelect (user: kc5tja tags: trunk)
04:55
[a5b58db554] Remove Verilog-based formal test bench for MStatus (user: kc5tja tags: trunk)
04:44
[00a555b8ef] Remove from nmigen import * in favor of explicit imports (user: kc5tja tags: trunk)
03:21
[c2e3819404] Thank you Luke Kenneth Casson Leighton for this contribution. This shows me both where I went wrong in my previous attempts to apply nmigen towards formal verification, but also a better interface to make formal tests run automatically than through a stack of mostly-but-not-exactly-identical Makefile rules. I will start evolving the codebase to use this new approach. (user: kc5tja tags: trunk)
2019-04-29
06:52
[d1cdbff14a] Updating spec and PSP (user: kc5tja tags: trunk)
2019-04-09
05:23
[6c559135a3] Add (M)CYCLE, (M)INSTRET (user: kc5tja tags: trunk)
01:16
[615dbc6e78] Implement MIP register (user: kc5tja tags: trunk)
2019-04-08
07:19
[e67e2d5951] Complete CSRU. No I/Os to outside world yet, though, but those can be added later. From CPU's POV, all CSRs are implemented and properly handle WLRL fields. (user: kc5tja tags: trunk)
00:30
[fcac6fca38] Remove commented old code. (user: kc5tja tags: trunk)
00:29
[6074d7325c] Convert MSTATUS and MIE to use MemCSR (user: kc5tja tags: trunk)
2019-04-07
22:57
[c0dba178f7] Generalize memory-only type CSRs. Some CSRs which have non-memory semantics can, in fact, use MemCSRs as a submodule, and just wrap CSR-specific logic around this. (user: kc5tja tags: trunk)
2019-03-25
08:15
[1629179d84] Begin proving mstatus (user: kc5tja tags: trunk)
06:09
[f311559092] Formally verify InputCSR (user: kc5tja tags: trunk)
05:17
[6facb8fbe2] Formally verify ConstantCSR (user: kc5tja tags: trunk)
04:32
[d460e67f4a] tighten CSRSelect properties (user: kc5tja tags: trunk)
04:24
[f96c5158b4] Formally prove CSRSelect (user: kc5tja tags: trunk)
2019-03-24
19:56
[aa1efe0a7d] Data output logic. (user: kc5tja tags: trunk)
2019-03-23
18:45
[f226214414] Implement MSTATUS. (user: kc5tja tags: trunk)
17:37
[e96a1d61c9] Bringing repo up to date, as I'm giving a demo at SVFIG. (user: kc5tja tags: trunk)
2019-03-18
08:25
[4c2460e8d1] Begin implementation of the CSR Unit. Holy heck, using nMigen for this was totally the right choice. The CSRU module is **tiny** compared to its equivalent Verilog. (user: kc5tja tags: trunk)
2019-03-16
02:45
[2dc9dd15f4] Spec and project data updates. (user: kc5tja tags: trunk)
2019-03-13
07:11
[04d68e52a6] Beginning specification work for the KCP53000B processor design. (user: kc5tja tags: trunk)
2018-11-26
18:16
[3989d347ab] SIA IS PROVEN! The core worked fine. The problem was a bug in my ROMA core instantiation. Celebration time!! (user: kc5tja tags: trunk)
07:36
[f70ab01418] Prove in hardware that the SIA core works. IT DOES. However, there is a bug when sending bytes with relatively few bits set on the low end of the byte (e.g., 0x05 becomes 0x0A on the receiver, while 0x51 remains 0x51 on the receiver). I genuinely have no idea how or why this is happening at this time. (user: kc5tja tags: trunk)
07:35
[315211fe32] Parameterize the SIA core. (user: kc5tja tags: trunk)
05:53
[8d2bf519df] Fucking reset circuitry gets me every time! (user: kc5tja tags: trunk)
01:34
[b06cdcafc5] First cut at a hardware integration test for the SIA (user: kc5tja tags: trunk)
2018-11-25
02:29
[5511953cec] Forgot to remove debugging change to default loopback settings (user: kc5tja tags: trunk)
02:03
[2867a12bc1] Integration test: SIA local loopback test passes! (user: kc5tja tags: trunk)
02:03
[8fe7daff6e] Bug fix: Draw the loopback control bits from the proper data lines. (user: kc5tja tags: trunk)
02:01
[f047e61a8d] Bug fix: make sure loopback control bits are accounted for in formal assertions. (user: kc5tja tags: trunk)
2018-11-01
17:58
[1dd9f6b5cf] WIP: Renovate sia_tilelink.v and properties.vf to work better with Verilator. HOWEVER, Verilator now cannot locate "verilated.h" for some reason. Even if I manually include its path as a -I parameter to gcc, it refuses to find it. NOTE: I'll need to apply these kinds of renovations to all the other Verilog sources in the SIA core, and quite possibly throughout the Kestrel-3 repository as well. UUGH! I hate Verilog so much after this. The Verilog spec is total garbage if nobody is going to bother to follow it. Many thanks to ZipCPU (Dan G.) for isolating what could be one of the biggest bugs of the Kestrel-3, and a major source of what's driving me crazy with this project. (user: kc5tja tags: trunk)
2018-10-31
05:59
[c72d29e3e8] Revise TB to match structure used by ZipCPU (user: kc5tja tags: trunk)
2018-10-30
17:33
[ef48c3f143] Remove uncompilable code (user: kc5tja tags: trunk)
17:14
[857710bfcf] WIP: SIA: Passes induction but not unit tests?! WTF?! I'm getting too old for this crap. (user: kc5tja tags: trunk)
2018-10-26
18:47
[74a8631b27] SIA: Adjust working paths (user: kc5tja tags: trunk)
18:40
[3d2b8fb5b2] Remove unnecessary subdirectories (user: kc5tja tags: trunk)
18:39
[9605232766] WIP: SIA: Clean up directory structure (user: kc5tja tags: trunk)
18:17
[eda0bdb81a] WIP: SIA: First unit test for SIA (user: kc5tja tags: trunk)
16:22
[caf59227ca] WIP: SIA: Top-level (user: kc5tja tags: trunk)
06:51
[ea401e4d06] SIA: Transmit engine seems to be complete. Next step: top-level. Again. (user: kc5tja tags: trunk)
06:24
[d1e65629f7] WIP: SIA: Integrate transmit engine baud rate generator. Having the BRG as a separate module made the top-level unnecessarily complex, as some signal wires were just not used, and others just not needed. Does not yet pass formal. (user: kc5tja tags: trunk)
2018-10-22
02:18
[40bc0dad6e] SIA: Why didn't the merge include the makefile? (user: kc5tja tags: trunk)
02:09
[f6bd84d868] Import roma core from formal branch (user: kc5tja tags: trunk)
02:03
[16aceea475] Merging did the wrong thing with the DMAC. Bring in the latest DMAC. (user: kc5tja tags: trunk)
01:57
[af53196bd7] Formal verification has proven itself as a viable development method. Merging into trunk. (user: kc5tja tags: trunk)
2018-08-29
00:59
[e19f2d7e5c] Attempt to add ROMA verification properties on my own (user: kc5tja tags: trunk)
2018-08-28
21:51
[3ded29d7df] Fixed the clock leak on ROMA core after adding FV to DMAC. Next step: figure out why only one bus transaction is taking place. (user: kc5tja tags: trunk)
21:51
[7756138d89] Fixed the clock leak on ROMA core after adding FV to DMAC. Next step: figure out why only one bus transaction is taking place. (user: kc5tja tags: trunk)
05:55
[0f3c9ade6a] Remove spurious Or operator (user: kc5tja tags: trunk)
05:42
[f2a9d73ac1] Make unit test pass for DMAC (user: kc5tja tags: trunk)
04:40
[eaace617c1] Fix commentary (user: kc5tja tags: trunk)
04:36
[db46c3c0e7] Introduce some formal verification for the DMAC (user: kc5tja tags: trunk)
01:19
[2795fa984f] ROMA + DMAC = working now, due to DDR clock buffer. (user: kc5tja tags: trunk)
2018-08-25
02:34
[1d81dbc235] ROMA: Fix data alignment bug. (user: kc5tja tags: trunk)
00:20
[a79aca60ee] Fix integration test MOSI/MISO assignment (user: kc5tja tags: trunk)
2018-08-24
05:33
[ed4beeb135] WIP: FPGA programs OK; flash programs OK; DMAC seems to be working OK; ROMA seems to be working OK; however, data read back is always $FF on the LEDs. This suggests either the CPLD is interfering with my communications somehow, OR, I'm botching the SPI protocol somehow. Unsure which yet. More research is needed. (user: kc5tja tags: trunk)
00:59
[3444a010e1] Refactor common definitions into shared headers (user: kc5tja tags: trunk)
2018-08-23
23:51
[d3867aab51] ROMA: Support back-to-back transactions (user: kc5tja tags: trunk)
23:29
[f7064f5df0] ROMA: Forgot to drive the CLK output (user: kc5tja tags: trunk)
23:25
[2bccfe58ef] ROMA: I think it is finished. (user: kc5tja tags: trunk)
23:10
[85e9538b39] Confirm proper data output (user: kc5tja tags: trunk)
22:48
[1181e5b5d7] ROMA: Proper D-channel handoff (user: kc5tja tags: trunk)
22:43
[e4574d60c9] Negate SPI Flash CS after 64 data bits read (user: kc5tja tags: trunk)
07:36
[a777854d78] ROMA: Send 21-bit dword-aligned address too (user: kc5tja tags: trunk)
07:20
[cffa191f94] ROMA: Send command byte on read request (user: kc5tja tags: trunk)
07:00
[0892ceaf82] ROMA: Recognize read request (user: kc5tja tags: trunk)
06:02
[768fc08020] ROMA: Slave A-channel first commit (user: kc5tja tags: trunk)
05:48
[e4318b055e] First commit for ROMA core. (user: kc5tja tags: trunk)
2018-08-17
19:47
[c47448ac7d] WIP: Trying to get E2 to build in new environment (user: kc5tja tags: trunk)
17:44
[fe4ca6880a] DXForth source tree (user: kc5tja tags: trunk)
17:39
[711ad764bd] DXForth binary generation (user: kc5tja tags: trunk)
17:38
[f76a09e9d5] Include path support for more sophisticated software builds. (user: kc5tja tags: trunk)