Kestrel-3

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50 most recent check-ins

2018-11-26
18:16
[3989d347ab] Leaf: SIA IS PROVEN! The core worked fine. The problem was a bug in my ROMA core instantiation. Celebration time!! (user: kc5tja tags: trunk)
07:36
[f70ab01418] Prove in hardware that the SIA core works. IT DOES. However, there is a bug when sending bytes with relatively few bits set on the low end of the byte (e.g., 0x05 becomes 0x0A on the receiver, while 0x51 remains 0x51 on the receiver). I genuinely have no idea how or why this is happening at this time. (user: kc5tja tags: trunk)
07:35
[315211fe32] Parameterize the SIA core. (user: kc5tja tags: trunk)
05:53
[8d2bf519df] Fucking reset circuitry gets me every time! (user: kc5tja tags: trunk)
01:34
[b06cdcafc5] First cut at a hardware integration test for the SIA (user: kc5tja tags: trunk)
2018-11-25
02:29
[5511953cec] Forgot to remove debugging change to default loopback settings (user: kc5tja tags: trunk)
02:03
[2867a12bc1] Integration test: SIA local loopback test passes! (user: kc5tja tags: trunk)
02:03
[8fe7daff6e] Bug fix: Draw the loopback control bits from the proper data lines. (user: kc5tja tags: trunk)
02:01
[f047e61a8d] Bug fix: make sure loopback control bits are accounted for in formal assertions. (user: kc5tja tags: trunk)
2018-11-01
17:58
[1dd9f6b5cf] WIP: Renovate sia_tilelink.v and properties.vf to work better with Verilator. HOWEVER, Verilator now cannot locate "verilated.h" for some reason. Even if I manually include its path as a -I parameter to gcc, it refuses to find it. NOTE: I'll need to apply these kinds of renovations to all the other Verilog sources in the SIA core, and quite possibly throughout the Kestrel-3 repository as well. UUGH! I hate Verilog so much after this. The Verilog spec is total garbage if nobody is going to bother to follow it. Many thanks to ZipCPU (Dan G.) for isolating what could be one of the biggest bugs of the Kestrel-3, and a major source of what's driving me crazy with this project. (user: kc5tja tags: trunk)
2018-10-31
05:59
[c72d29e3e8] Revise TB to match structure used by ZipCPU (user: kc5tja tags: trunk)
2018-10-30
17:33
[ef48c3f143] Remove uncompilable code (user: kc5tja tags: trunk)
17:14
[857710bfcf] WIP: SIA: Passes induction but not unit tests?! WTF?! I'm getting too old for this crap. (user: kc5tja tags: trunk)
2018-10-26
18:47
[74a8631b27] SIA: Adjust working paths (user: kc5tja tags: trunk)
18:40
[3d2b8fb5b2] Remove unnecessary subdirectories (user: kc5tja tags: trunk)
18:39
[9605232766] WIP: SIA: Clean up directory structure (user: kc5tja tags: trunk)
18:17
[eda0bdb81a] WIP: SIA: First unit test for SIA (user: kc5tja tags: trunk)
16:22
[caf59227ca] WIP: SIA: Top-level (user: kc5tja tags: trunk)
06:51
[ea401e4d06] SIA: Transmit engine seems to be complete. Next step: top-level. Again. (user: kc5tja tags: trunk)
06:24
[d1e65629f7] WIP: SIA: Integrate transmit engine baud rate generator. Having the BRG as a separate module made the top-level unnecessarily complex, as some signal wires were just not used, and others just not needed. Does not yet pass formal. (user: kc5tja tags: trunk)
2018-10-22
02:18
[40bc0dad6e] SIA: Why didn't the merge include the makefile? (user: kc5tja tags: trunk)
02:09
[f6bd84d868] Import roma core from formal branch (user: kc5tja tags: trunk)
02:03
[16aceea475] Merging did the wrong thing with the DMAC. Bring in the latest DMAC. (user: kc5tja tags: trunk)
01:57
[af53196bd7] Formal verification has proven itself as a viable development method. Merging into trunk. (user: kc5tja tags: trunk)
01:37
[bcb48b6e07] Closed-Leaf: SIA: IRQ support! (user: kc5tja tags: formal)
00:54
[bfd80199ba] SIA: Implement INTENA register (user: kc5tja tags: formal)
2018-10-21
23:41
[49b4a6be70] Expose loopback controls for external circuitry (top level perhaps) (user: kc5tja tags: formal)
23:24
[237f455dc6] SIA: Map loopback control bits into BAUD register (user: kc5tja tags: formal)
21:02
[df3f069cc2] Map receiver status bits and data to their respective registers. (user: kc5tja tags: formal)
2018-10-20
22:38
[3de7c2bf82] SIA: Revise block diagram for end result (user: kc5tja tags: formal)
22:20
[eeabb18974] Removed edge-sensitivity and support for external clocks, and made receiver sampling unconditionally plesiochronous. This eliminated a number of edge-case bugs from the receiver that hinted at some serious noise sensitivity issues. The SIA is thus now 100% a UART, with no synchronous reception capabilities at all. (user: kc5tja tags: formal)
2018-10-18
18:19
[5aa0d07ad9] SIA: Forgot to include SBY file. (user: kc5tja tags: formal)
07:01
[eb7b249c0b] SIA: valid and overrun bits must clear when reading from the data register (user: kc5tja tags: formal)
06:23
[50ec70df3f] SIA: Make sure the overrun flag works as expected (user: kc5tja tags: formal)
06:20
[ae7910af5b] SIA: Make sure o_rxd_valid asserts upon receipt of data (user: kc5tja tags: formal)
06:16
[dd7b7eb8d3] SIA: capture shift register contents upon completion of a frame (user: kc5tja tags: formal)
06:07
[0c8baa992f] SIA: Make sure frame detection is a pulse signal, not a level signal. (user: kc5tja tags: formal)
06:04
[5811734861] SIA: Detect when a frame is received (user: kc5tja tags: formal)
05:45
[aa82c9893b] SIA: Ensures the sample counter decrements when it is supposed to. (user: kc5tja tags: formal)
05:35
[12632108f0] SIA: Ensure sampleCtr is properly set in between characters (user: kc5tja tags: formal)
05:29
[9c0b76c048] SIA: Make sure we maintain plesiosynchronous sampling in the absence of edges (user: kc5tja tags: formal)
05:25
[41b6879592] SIA: Make sure samples happen in the middle of the bit cell after an edge is detected (user: kc5tja tags: formal)
05:20
[cb67ef073d] SIA: Sample counter reset behavior (user: kc5tja tags: formal)
05:13
[f7adb458b1] SIA: Tap the correct input for the shift register (user: kc5tja tags: formal)
05:03
[44ec5e4f5e] SIA: Make sure shiftRegister shifts in the correct direction (user: kc5tja tags: formal)
2018-10-16
17:20
[69de6d6c74] SIA: BMC passes for receiver's bit counter. (user: kc5tja tags: formal)
15:22
[e0a423cfd0] Empty properties.vf file (user: kc5tja tags: formal)
05:58
[ffb41dee02] SIA: Import source code from older SIA implementation, and simplify and document it a whole lot better. Preparing to insert properties as well. NOTE: This module has been simplified from the original SIA receiver logic. It cannot handle anything other than 8N1 serial frames. It's easy enough to restore the missing functionality, but it would require more SIA registers. Since current software does not make use of this functionality, and depends upon the SIA defaulting to 8N1 upon reset, I just decided to hardwire as much as I could. Adding registers can be done later, when it's actually justified. (user: kc5tja tags: formal)
2018-10-14
20:08
[6654e09566] Tickler README (user: kc5tja tags: formal)
01:07
[077f056270] Automate formal verification for SIA (user: kc5tja tags: formal)