Kestrel-3

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50 most recent check-ins

2019-06-06
07:41
[daf647810c] Leaf: update psp (user: kc5tja tags: trunk)
07:39
[7170d9c66c] Complete trunk register file source indices logic. (user: kc5tja tags: trunk)
07:19
[c387b96556] Add SUM_REQ, but I renamed it to CU_READ_VALUES. When asserted, it tells the CU when to capture the values of the register file on the trunk's register data ports. (user: kc5tja tags: trunk)
03:13
[2e36a268b3] When GO_READ is asserted by the picker, drop out of read state. (user: kc5tja tags: trunk)
2019-06-04
15:40
[87d90f5c93] WIP: FU logic recognizes when function units broadcast results on the trunk. Keeps track of operand available status. Drives READ_REQ signal when the FU feels all operands are now ready. (user: kc5tja tags: trunk)
2019-06-02
22:38
[2d67e26722] initial import for FU logic (user: kc5tja tags: trunk)
22:34
[e3c8c82fe7] Relabel some of the CU signals for easier recall of who drives them (user: kc5tja tags: trunk)
06:12
[3425f3c9f4] psp update (user: kc5tja tags: trunk)
05:28
[0c5c321cf6] WIP! This completes the add/subtract logic for the add/store computation unit. The precise needs of the "store" logic will be dictated by how the state machine in the function unit is implemented, so I'll cross that bridge when I get there. (user: kc5tja tags: trunk)
03:16
[46868584f7] WIP: First CDC 6600-inspired add/store computation unit. Experimental (user: kc5tja tags: trunk)
2019-05-28
01:00
[d7b385618d] Pass I port D channel error signal through to IXU for synchronous trap processing (user: kc5tja tags: trunk)
00:44
[d23d900a8b] Remember to double-check the lowest 2 address bits (user: kc5tja tags: trunk)
00:40
[f37147ffb1] Relabel interfaces properly; expose iq_flush (user: kc5tja tags: trunk)
00:27
[16b97e0e8b] Jump request and ack interface (user: kc5tja tags: trunk)
2019-05-27
22:53
[2dbe6f9e6d] Implement o_iq_valid handshake signal. Note that it is pulsed!! (See comments in code for more details.) (user: kc5tja tags: trunk)
2019-05-26
01:37
[23a3a9c2af] iq_address and iq_inst_addr implemented. Confirmed proper word routing from the fetched dword. I need to double-check proper handshaking next (e.g., iq_ready and iq_valid), and after that is done, work on the control flow functionality. (user: kc5tja tags: trunk)
2019-05-06
01:41
[e91ccded29] Finished IFU A-channel for instruction fetch port (TileLink). (user: kc5tja tags: trunk)
2019-05-05
07:51
[e17b606295] Makefile update to remove old ilang files (user: kc5tja tags: trunk)
07:50
[33a2716e57] Support the byte lane select mask (user: kc5tja tags: trunk)
07:34
[5c7b25760b] update psp (user: kc5tja tags: trunk)
07:20
[af1995818c] B/c the fetch_counter was treated as an anonymous input port to the module, allowing sby to tweak its value. Very unintuitive!! (user: kc5tja tags: trunk)
07:17
[3a96327a8f] WIP: Why u no work? Fails induction for unknown reasons (user: kc5tja tags: trunk)
03:57
[866dcdadac] update psp (user: kc5tja tags: trunk)
03:56
[3018838aa9] Initial IFU code (user: kc5tja tags: trunk)
2019-05-04
15:54
[9f51a63046] PSP update and spec update (user: kc5tja tags: trunk)
2019-05-02
22:34
[51b29796b7] Consolidate tests into per-module tests (user: kc5tja tags: trunk)
22:03
[13a75afbcd] Use nmigen version of tools.py (more maintainable) (user: kc5tja tags: trunk)
21:53
[c8c8464c5e] Migrate tests for UpCounterCSR to nmigen (user: kc5tja tags: trunk)
18:30
[c09510ecfd] Migrate MemCSR tests to nmigen (user: kc5tja tags: trunk)
17:52
[d38e951c0e] Augment clean target to account for nmigen's spec_xxx directories (user: kc5tja tags: trunk)
17:50
[09291e359f] Migrate InputCSR tests to nmigen (user: kc5tja tags: trunk)
17:30
[c216582c93] Migrate tests for ConstantCSR to nmigen (user: kc5tja tags: trunk)
05:23
[138c5505a1] Remove dead code (user: kc5tja tags: trunk)
05:22
[0e9f6538b4] Convert formal testbench to nmigen for CSRSelect (user: kc5tja tags: trunk)
04:55
[a5b58db554] Remove Verilog-based formal test bench for MStatus (user: kc5tja tags: trunk)
04:44
[00a555b8ef] Remove from nmigen import * in favor of explicit imports (user: kc5tja tags: trunk)
03:21
[c2e3819404] Thank you Luke Kenneth Casson Leighton for this contribution. This shows me both where I went wrong in my previous attempts to apply nmigen towards formal verification, but also a better interface to make formal tests run automatically than through a stack of mostly-but-not-exactly-identical Makefile rules. I will start evolving the codebase to use this new approach. (user: kc5tja tags: trunk)
2019-04-29
06:52
[d1cdbff14a] Updating spec and PSP (user: kc5tja tags: trunk)
2019-04-09
05:23
[6c559135a3] Add (M)CYCLE, (M)INSTRET (user: kc5tja tags: trunk)
01:16
[615dbc6e78] Implement MIP register (user: kc5tja tags: trunk)
2019-04-08
07:19
[e67e2d5951] Complete CSRU. No I/Os to outside world yet, though, but those can be added later. From CPU's POV, all CSRs are implemented and properly handle WLRL fields. (user: kc5tja tags: trunk)
00:30
[fcac6fca38] Remove commented old code. (user: kc5tja tags: trunk)
00:29
[6074d7325c] Convert MSTATUS and MIE to use MemCSR (user: kc5tja tags: trunk)
2019-04-07
22:57
[c0dba178f7] Generalize memory-only type CSRs. Some CSRs which have non-memory semantics can, in fact, use MemCSRs as a submodule, and just wrap CSR-specific logic around this. (user: kc5tja tags: trunk)
2019-03-25
08:15
[1629179d84] Begin proving mstatus (user: kc5tja tags: trunk)
06:09
[f311559092] Formally verify InputCSR (user: kc5tja tags: trunk)
05:17
[6facb8fbe2] Formally verify ConstantCSR (user: kc5tja tags: trunk)
04:32
[d460e67f4a] tighten CSRSelect properties (user: kc5tja tags: trunk)
04:24
[f96c5158b4] Formally prove CSRSelect (user: kc5tja tags: trunk)
2019-03-24
19:56
[aa1efe0a7d] Data output logic. (user: kc5tja tags: trunk)