ByteLink
This is my attempt at exposing the TileLink v1.7 TL-UL specification out over just two PMOD 2x6 ports. When clocked at 25MHz, best-case throughput should reach 4.5MB/s, which for a 640x480 16-color display, should be good for 29 frames per second.
This interconnect is not intended to be switched over a larger fabric. Rather, it's designed to meet a very specific need.
Except in the case of errors,
all data transactions take either
28 clock cycles,
30 clock cycles,
34 clock cycles,
or 42 clock cycles to complete
depending on the ss (payload size) field:
ss Size Bits
00 Byte 8
01 Half-word 16
10 Word 32
11 Double-word 64
Interconnect Signals
| Signal Name | CPU Card | I/O Card | Description |
|---|---|---|---|
| A0-A3 | OUT | IN | 4-bit A-channel packet data bus |
| ACLK | OUT | IN | A-channel clock (25MHz) |
| AFRAME | OUT | IN | A-channel message boundary indicator |
| B0-B3 | IN | OUT | 4-bit B-channel packet data bus |
| BCLK | IN | OUT | B-channel clock (25MHz) |
| BFRAME | IN | OUT | B-channel message boundary indicator |
NOTE: When sending data, Nyb0 is sent first, then Nyb1.
This generally follows the RISC-V convention of little-endian formats.
The xFRAME signal asserts only when sending Nyb0 of the first byte of a new packet.
Message Formats
GET
Nyb1 Nyb0
BYTE 1 00.. 0... Must be zero
..ss .... Size field
.... .opc Opcode (see TileLink spec)
BYTE 2 tttt tttt Transaction ID
BYTE 3 mmmm mmmm Read Mask (Unused)
BYTE 4 aaaa a... Address bits 0-7
.... .000 Must be zero
BYTE 5 aaaa aaaa Address bits 8-15
BYTE 6 aaaa aaaa Address bits 16-23
BYTE 7 aaaa aaaa Address bits 24-31
BYTE 8 aaaa aaaa Address bits 32-39
BYTE 9 aaaa aaaa Address bits 40-47
BYTE 10 aaaa aaaa Address bits 48-55
BYTE 11 aaaa aaaa Address bits 56-63
PUT PARTIAL and PUT FULL
Nyb1 Nyb0
BYTE 1 00.. 0... Must be zero
..ss .... Size field
.... .opc Opcode (see TileLink spec)
BYTE 2 tttt tttt Transaction ID
BYTE 3 mmmm mmmm Write Mask
BYTE 4 aaaa a... Address bits 0-7
.... .000 Must be zero
BYTE 5 aaaa aaaa Address bits 8-15
BYTE 6 aaaa aaaa Address bits 16-23
BYTE 7 aaaa aaaa Address bits 24-31
BYTE 8 aaaa aaaa Address bits 32-39
BYTE 9 aaaa aaaa Address bits 40-47
BYTE 10 aaaa aaaa Address bits 48-55
BYTE 11 aaaa aaaa Address bits 56-63
BYTE 12 dddd dddd Data bits 0-7 (required)
BYTE 13 dddd dddd Data bits 8-15 (only if ss >= 1)
BYTE 14 dddd dddd Data bits 16-23 (only if ss >= 2)
BYTE 15 dddd dddd Data bits 24-31 (only if ss >= 2)
BYTE 16 dddd dddd Data bits 32-39 (only if ss = 3)
BYTE 17 dddd dddd Data bits 40-47 (only if ss = 3)
BYTE 18 dddd dddd Data bits 48-55 (only if ss = 3)
BYTE 19 dddd dddd Data bits 56-63 (only if ss = 3)
ACK
BYTE 1 0... .... Must be zero
.E.. .... Set if error; clear otherwise
..ss .... Size field
.... 1... Must be one
.... .opc Opcode (see TileLink spec)
BYTE 2 tttt tttt Transaction ID
ACK DATA
BYTE 1 0... .... Must be zero
.E.. .... Set if error; clear otherwise
..ss .... Size field
.... 1... Must be one
.... .opc Opcode (see TileLink spec)
BYTE 2 tttt tttt Transaction ID
BYTE 3 dddd dddd Data bits 0-7 (required)
BYTE 4 dddd dddd Data bits 8-15 (only if ss >= 1)
BYTE 5 dddd dddd Data bits 16-23 (only if ss >= 2)
BYTE 6 dddd dddd Data bits 24-31 (only if ss >= 2)
BYTE 7 dddd dddd Data bits 32-39 (only if ss = 3)
BYTE 8 dddd dddd Data bits 40-47 (only if ss = 3)
BYTE 9 dddd dddd Data bits 48-55 (only if ss = 3)
BYTE 10 dddd dddd Data bits 56-63 (only if ss = 3)