Kestrel-3

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50 most recent timeline items

2018-09-16
23:09 • Changes to wiki page Kestrel-3 (user: kc5tja)
23:08 • Changes to wiki page Ruminations on Expanding the Kestrel-3 (user: kc5tja)
2018-09-11
17:06 • Changes to wiki page Ruminations on Expanding the Kestrel-3 (user: kc5tja)
2018-09-10
17:40 • Changes to wiki page Ruminations on Expanding the Kestrel-3 (user: kc5tja)
16:56 • Changes to wiki page Ruminations on Expanding the Kestrel-3 (user: kc5tja)
2018-09-06
04:47
[23614639e5] Leaf: SIA:Implement the register backing BAUD and support for specific byte-lanes. Also, reduce default width of rate generator's divisor to match the width of the BAUD register. (user: kc5tja, tags: formal)
2018-09-05
03:19
[d2d579a5a2] Add default nettypes (user: kc5tja, tags: formal)
03:15
[f4ede39e18] SIA:WIP:Fix inductive proof failure (user: kc5tja, tags: formal)
01:14
[52809c12cd] SIA: WIP: unsure why it doesn't pass formal checks in "prove" mode (user: kc5tja, tags: formal)
2018-09-04
02:49
[4276cebda5] SIA:TileLink coupling (WIP) (user: kc5tja, tags: formal)
2018-09-03
17:36
[2149cd86a8] SIA: Controlling registers (just BAUD for now) (user: kc5tja, tags: formal)
06:35 • Changes to wiki page Memory Map (user: kc5tja)
06:23 • Changes to wiki page Memory Map (user: kc5tja)
06:06 • Changes to wiki page Memory Map (user: kc5tja)
06:01 • Changes to wiki page Memory Map (user: kc5tja)
05:43 • Changes to wiki page Memory Map (user: kc5tja)
02:25 • Changes to wiki page Memory Map (user: kc5tja)
2018-09-02
02:04
[d06bf263a4] SIA:TX:Implement the transmitter shift register logic. (user: kc5tja, tags: formal)
2018-09-01
17:49
[0b911e8ec0] First module for transmit engine (user: kc5tja, tags: formal)
2018-08-31
06:34
[088d1cf570] Rate generator intended for use with the SIA implementation (user: kc5tja, tags: formal)
03:32
[2c5d0f5fce] SIA: Rate Generator (user: kc5tja, tags: formal)
01:56
[b3f95194cf] Clearer name to describe intent of the "core". (user: kc5tja, tags: formal)
2018-08-30
18:11
[d5debe2752] Per ZipCPU's suggestion, I didn't need the initial block if I qualified some of my assertions more thoroughly. (user: kc5tja, tags: formal)
05:51 • Changes to wiki page Development Strategy (user: kc5tja)
04:57
[b014c7b07f] ROMA: Formal verification of TileLink bus seems to be complete. (user: kc5tja, tags: formal)
00:53 • Edit [f1b71290ae1ee82a|f1b71290ae]: Move to branch formal. (user: kc5tja)
2018-08-29
18:44
[2f8acc4498] WIP ROMA: Qualify A-channel transaction by comparing opcode. Verify that o_d_valid should be negated for as long as we lack a read result. Remove reg qualifier from all signals we "assign" to. Generate o_a_ready based on state of bits_so_far. Passes bmc; fails to prove inductively. Cause is o_d_valid && i_d_ready true while not engaged in an actual transaction. Cannot figure out how to tell prover that this is an impossible condition. (user: kc5tja, tags: formal)
06:57
[2da2614d5c] Enforce proper handling of o_a_ready (user: kc5tja, tags: formal)
05:38
[f1b71290ae] First set of formal properties for ROMA core (user: kc5tja, tags: formal)
04:56
[c5528419c2] Leaf: Create new branch named "formal" (user: kc5tja, tags: formal)
00:59
[e19f2d7e5c] Leaf: Attempt to add ROMA verification properties on my own (user: kc5tja, tags: trunk)
2018-08-28
21:51
[3ded29d7df] Fixed the clock leak on ROMA core after adding FV to DMAC. Next step: figure out why only one bus transaction is taking place. (user: kc5tja, tags: trunk)
21:51
[7756138d89] Fixed the clock leak on ROMA core after adding FV to DMAC. Next step: figure out why only one bus transaction is taking place. (user: kc5tja, tags: trunk)
05:55
[0f3c9ade6a] Remove spurious Or operator (user: kc5tja, tags: trunk)
05:42
[f2a9d73ac1] Make unit test pass for DMAC (user: kc5tja, tags: trunk)
04:40
[eaace617c1] Fix commentary (user: kc5tja, tags: trunk)
04:36
[db46c3c0e7] Introduce some formal verification for the DMAC (user: kc5tja, tags: trunk)
01:19
[2795fa984f] ROMA + DMAC = working now, due to DDR clock buffer. (user: kc5tja, tags: trunk)
2018-08-25
02:34
[1d81dbc235] ROMA: Fix data alignment bug. (user: kc5tja, tags: trunk)
00:20
[a79aca60ee] Fix integration test MOSI/MISO assignment (user: kc5tja, tags: trunk)
2018-08-24
05:33
[ed4beeb135] WIP: FPGA programs OK; flash programs OK; DMAC seems to be working OK; ROMA seems to be working OK; however, data read back is always $FF on the LEDs. This suggests either the CPLD is interfering with my communications somehow, OR, I'm botching the SPI protocol somehow. Unsure which yet. More research is needed. (user: kc5tja, tags: trunk)
00:59
[3444a010e1] Refactor common definitions into shared headers (user: kc5tja, tags: trunk)
2018-08-23
23:51
[d3867aab51] ROMA: Support back-to-back transactions (user: kc5tja, tags: trunk)
23:29
[f7064f5df0] ROMA: Forgot to drive the CLK output (user: kc5tja, tags: trunk)
23:25
[2bccfe58ef] ROMA: I think it is finished. (user: kc5tja, tags: trunk)
23:10
[85e9538b39] Confirm proper data output (user: kc5tja, tags: trunk)
22:48
[1181e5b5d7] ROMA: Proper D-channel handoff (user: kc5tja, tags: trunk)
22:43
[e4574d60c9] Negate SPI Flash CS after 64 data bits read (user: kc5tja, tags: trunk)
07:36
[a777854d78] ROMA: Send 21-bit dword-aligned address too (user: kc5tja, tags: trunk)
07:20
[cffa191f94] ROMA: Send command byte on read request (user: kc5tja, tags: trunk)