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3 check-ins using file cores/dmac/rtl/verilog/dmac.v version ab023ea0e3
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2018-08-28
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| 21:51 | Fixed the clock leak on ROMA core after adding FV to DMAC. Next step: figure out why only one bus transaction is taking place. check-in: 3ded29d7df user: kc5tja tags: trunk | |
| 21:51 | Fixed the clock leak on ROMA core after adding FV to DMAC. Next step: figure out why only one bus transaction is taking place. check-in: 7756138d89 user: kc5tja tags: trunk | |
| 05:55 | Remove spurious Or operator check-in: 0f3c9ade6a user: kc5tja tags: trunk | |