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15 check-ins using file cores/cpu/spec.org version 99a1e03db5
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2019-04-09
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| 05:23 | Add (M)CYCLE, (M)INSTRET check-in: 6c559135a3 user: kc5tja tags: trunk | |
| 01:16 | Implement MIP register check-in: 615dbc6e78 user: kc5tja tags: trunk | |
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2019-04-08
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| 07:19 | Complete CSRU. No I/Os to outside world yet, though, but those can be added later. From CPU's POV, all CSRs are implemented and properly handle WLRL fields. check-in: e67e2d5951 user: kc5tja tags: trunk | |
| 00:30 | Remove commented old code. check-in: fcac6fca38 user: kc5tja tags: trunk | |
| 00:29 | Convert MSTATUS and MIE to use MemCSR check-in: 6074d7325c user: kc5tja tags: trunk | |
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2019-04-07
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| 22:57 | Generalize memory-only type CSRs. Some CSRs which have non-memory semantics can, in fact, use MemCSRs as a submodule, and just wrap CSR-specific logic around this. check-in: c0dba178f7 user: kc5tja tags: trunk | |
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2019-03-25
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| 08:15 | Begin proving mstatus check-in: 1629179d84 user: kc5tja tags: trunk | |
| 06:09 | Formally verify InputCSR check-in: f311559092 user: kc5tja tags: trunk | |
| 05:17 | Formally verify ConstantCSR check-in: 6facb8fbe2 user: kc5tja tags: trunk | |
| 04:32 | tighten CSRSelect properties check-in: d460e67f4a user: kc5tja tags: trunk | |
| 04:24 | Formally prove CSRSelect check-in: f96c5158b4 user: kc5tja tags: trunk | |
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2019-03-24
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| 19:56 | Data output logic. check-in: aa1efe0a7d user: kc5tja tags: trunk | |
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2019-03-23
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| 18:45 | Implement MSTATUS. check-in: f226214414 user: kc5tja tags: trunk | |
| 17:37 | Bringing repo up to date, as I'm giving a demo at SVFIG. check-in: e96a1d61c9 user: kc5tja tags: trunk | |
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2019-03-18
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| 08:25 | Begin implementation of the CSR Unit. Holy heck, using nMigen for this was totally the right choice. The CSRU module is **tiny** compared to its equivalent Verilog. check-in: 4c2460e8d1 user: kc5tja tags: trunk | |