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9 check-ins using file cores/roma/rtl/verilog/roma.v version 36b2b8aad1
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2018-08-29
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| 04:56 | Create new branch named "formal" Leaf check-in: c5528419c2 user: kc5tja tags: formal | |
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2018-08-28
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| 21:51 | Fixed the clock leak on ROMA core after adding FV to DMAC. Next step: figure out why only one bus transaction is taking place. check-in: 3ded29d7df user: kc5tja tags: trunk | |
| 21:51 | Fixed the clock leak on ROMA core after adding FV to DMAC. Next step: figure out why only one bus transaction is taking place. check-in: 7756138d89 user: kc5tja tags: trunk | |
| 05:55 | Remove spurious Or operator check-in: 0f3c9ade6a user: kc5tja tags: trunk | |
| 05:42 | Make unit test pass for DMAC check-in: f2a9d73ac1 user: kc5tja tags: trunk | |
| 04:40 | Fix commentary check-in: eaace617c1 user: kc5tja tags: trunk | |
| 04:36 | Introduce some formal verification for the DMAC check-in: db46c3c0e7 user: kc5tja tags: trunk | |
| 01:19 | ROMA + DMAC = working now, due to DDR clock buffer. check-in: 2795fa984f user: kc5tja tags: trunk | |
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2018-08-25
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| 02:34 | ROMA: Fix data alignment bug. check-in: 1d81dbc235 user: kc5tja tags: trunk | |