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50 most recent check-ins that include changes to files matching 'cores/sia/*'
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2018-11-26
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| 07:35 | Parameterize the SIA core. check-in: 315211fe32 user: kc5tja tags: trunk | |
| 01:34 | First cut at a hardware integration test for the SIA check-in: b06cdcafc5 user: kc5tja tags: trunk | |
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2018-11-25
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| 02:29 | Forgot to remove debugging change to default loopback settings check-in: 5511953cec user: kc5tja tags: trunk | |
| 02:03 | Integration test: SIA local loopback test passes! check-in: 2867a12bc1 user: kc5tja tags: trunk | |
| 02:03 | Bug fix: Draw the loopback control bits from the proper data lines. check-in: 8fe7daff6e user: kc5tja tags: trunk | |
| 02:01 | Bug fix: make sure loopback control bits are accounted for in formal assertions. check-in: f047e61a8d user: kc5tja tags: trunk | |
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2018-11-01
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| 17:58 | WIP: Renovate sia_tilelink.v and properties.vf to work better with Verilator. HOWEVER, Verilator now cannot locate "verilated.h" for some reason. Even if I manually include its path as a -I parameter to gcc, it refuses to find it. NOTE: I'll need to apply these kinds of renovations to all the other Verilog sources in the SIA core, and quite possibly throughout the Kestrel-3 repository as well. UUGH! I hate Verilog so much after this. The Verilog spec is total garbage if nobody is going to bother to follow it. Many thanks to ZipCPU (Dan G.) for isolating what could be one of the biggest bugs of the Kestrel-3, and a major source of what's driving me crazy with this project. check-in: 1dd9f6b5cf user: kc5tja tags: trunk | |
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2018-10-31
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| 05:59 | Revise TB to match structure used by ZipCPU check-in: c72d29e3e8 user: kc5tja tags: trunk | |
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2018-10-30
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| 17:33 | Remove uncompilable code check-in: ef48c3f143 user: kc5tja tags: trunk | |
| 17:14 | WIP: SIA: Passes induction but not unit tests?! WTF?! I'm getting too old for this crap. check-in: 857710bfcf user: kc5tja tags: trunk | |
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2018-10-26
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| 18:47 | SIA: Adjust working paths check-in: 74a8631b27 user: kc5tja tags: trunk | |
| 18:40 | Remove unnecessary subdirectories check-in: 3d2b8fb5b2 user: kc5tja tags: trunk | |
| 18:39 | WIP: SIA: Clean up directory structure check-in: 9605232766 user: kc5tja tags: trunk | |
| 18:17 | WIP: SIA: First unit test for SIA check-in: eda0bdb81a user: kc5tja tags: trunk | |
| 16:22 | WIP: SIA: Top-level check-in: caf59227ca user: kc5tja tags: trunk | |
| 06:51 | SIA: Transmit engine seems to be complete. Next step: top-level. Again. check-in: ea401e4d06 user: kc5tja tags: trunk | |
| 06:24 | WIP: SIA: Integrate transmit engine baud rate generator. Having the BRG as a separate module made the top-level unnecessarily complex, as some signal wires were just not used, and others just not needed. Does not yet pass formal. check-in: d1e65629f7 user: kc5tja tags: trunk | |
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2018-10-22
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| 02:18 | SIA: Why didn't the merge include the makefile? check-in: 40bc0dad6e user: kc5tja tags: trunk | |
| 01:57 | Formal verification has proven itself as a viable development method. Merging into trunk. check-in: af53196bd7 user: kc5tja tags: trunk | |
| 01:37 | SIA: IRQ support! Closed-Leaf check-in: bcb48b6e07 user: kc5tja tags: formal | |
| 00:54 | SIA: Implement INTENA register check-in: bfd80199ba user: kc5tja tags: formal | |
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2018-10-21
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| 23:41 | Expose loopback controls for external circuitry (top level perhaps) check-in: 49b4a6be70 user: kc5tja tags: formal | |
| 23:24 | SIA: Map loopback control bits into BAUD register check-in: 237f455dc6 user: kc5tja tags: formal | |
| 21:02 | Map receiver status bits and data to their respective registers. check-in: df3f069cc2 user: kc5tja tags: formal | |
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2018-10-20
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| 22:38 | SIA: Revise block diagram for end result check-in: 3de7c2bf82 user: kc5tja tags: formal | |
| 22:20 | Removed edge-sensitivity and support for external clocks, and made receiver sampling unconditionally plesiochronous. This eliminated a number of edge-case bugs from the receiver that hinted at some serious noise sensitivity issues. The SIA is thus now 100% a UART, with no synchronous reception capabilities at all. check-in: eeabb18974 user: kc5tja tags: formal | |
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2018-10-18
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| 18:19 | SIA: Forgot to include SBY file. check-in: 5aa0d07ad9 user: kc5tja tags: formal | |
| 07:01 | SIA: valid and overrun bits must clear when reading from the data register check-in: eb7b249c0b user: kc5tja tags: formal | |
| 06:23 | SIA: Make sure the overrun flag works as expected check-in: 50ec70df3f user: kc5tja tags: formal | |
| 06:20 | SIA: Make sure o_rxd_valid asserts upon receipt of data check-in: ae7910af5b user: kc5tja tags: formal | |
| 06:16 | SIA: capture shift register contents upon completion of a frame check-in: dd7b7eb8d3 user: kc5tja tags: formal | |
| 06:07 | SIA: Make sure frame detection is a pulse signal, not a level signal. check-in: 0c8baa992f user: kc5tja tags: formal | |
| 06:04 | SIA: Detect when a frame is received check-in: 5811734861 user: kc5tja tags: formal | |
| 05:45 | SIA: Ensures the sample counter decrements when it is supposed to. check-in: aa82c9893b user: kc5tja tags: formal | |
| 05:35 | SIA: Ensure sampleCtr is properly set in between characters check-in: 12632108f0 user: kc5tja tags: formal | |
| 05:29 | SIA: Make sure we maintain plesiosynchronous sampling in the absence of edges check-in: 9c0b76c048 user: kc5tja tags: formal | |
| 05:25 | SIA: Make sure samples happen in the middle of the bit cell after an edge is detected check-in: 41b6879592 user: kc5tja tags: formal | |
| 05:20 | SIA: Sample counter reset behavior check-in: cb67ef073d user: kc5tja tags: formal | |
| 05:13 | SIA: Tap the correct input for the shift register check-in: f7adb458b1 user: kc5tja tags: formal | |
| 05:03 | SIA: Make sure shiftRegister shifts in the correct direction check-in: 44ec5e4f5e user: kc5tja tags: formal | |
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2018-10-16
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| 17:20 | SIA: BMC passes for receiver's bit counter. check-in: 69de6d6c74 user: kc5tja tags: formal | |
| 15:22 | Empty properties.vf file check-in: e0a423cfd0 user: kc5tja tags: formal | |
| 05:58 | SIA: Import source code from older SIA implementation, and simplify and document it a whole lot better. Preparing to insert properties as well. NOTE: This module has been simplified from the original SIA receiver logic. It cannot handle anything other than 8N1 serial frames. It's easy enough to restore the missing functionality, but it would require more SIA registers. Since current software does not make use of this functionality, and depends upon the SIA defaulting to 8N1 upon reset, I just decided to hardwire as much as I could. Adding registers can be done later, when it's actually justified. check-in: ffb41dee02 user: kc5tja tags: formal | |
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2018-10-14
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| 20:08 | Tickler README check-in: 6654e09566 user: kc5tja tags: formal | |
| 01:07 | Automate formal verification for SIA check-in: 077f056270 user: kc5tja tags: formal | |
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2018-10-06
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| 06:27 | Expose the baud rate divisor to the interface check-in: 4707d76538 user: kc5tja tags: formal | |
| 06:18 | Expose data written to TXOUT for use by shift register logic check-in: 87571690eb user: kc5tja tags: formal | |
| 04:35 | Comments! check-in: df6214cf7d user: kc5tja tags: formal | |
| 02:13 | Add required conditions to make it pass induction. check-in: e351f5396b user: kc5tja tags: formal | |
| 01:03 | Try to use a saturating counter to see if it will make induction pass. check-in: 60d4a58321 user: kc5tja tags: formal | |