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50 most recent check-ins that include changes to files matching 'cores/cpu/*'
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2019-08-05
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| 07:53 | Bug fix: branch displacement was missing a bit check-in: 797fafc3c9 user: kc5tja tags: trunk | |
| 06:31 | writeback logic first pass implemented. check-in: 0708c27675 user: kc5tja tags: trunk | |
| 03:44 | SRLI and SRAI -- this completes OP-IMM check-in: b705e135a7 user: kc5tja tags: trunk | |
| 03:23 | AND, OR, XOR check-in: 83070c8d95 user: kc5tja tags: trunk | |
| 03:21 | Bug fix for SLTI: -4 < 4 would fail test check-in: 26f3c58373 user: kc5tja tags: trunk | |
| 03:02 | SLTI and SLTUI check-in: fe12c3b40e user: kc5tja tags: trunk | |
| 02:49 | SLLI implemented in the IXU check-in: d265210c64 user: kc5tja tags: trunk | |
| 02:30 | ANDI instruction works. check-in: b0c8e8b48a user: kc5tja tags: trunk | |
| 01:20 | Initial integration of ALU into IXU; no tests yet check-in: 3d81d8061e user: kc5tja tags: trunk | |
| 00:11 | Simplify the ALU code significantly check-in: 84a26d5484 user: kc5tja tags: trunk | |
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2019-08-04
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| 21:41 | Introduce (untested) ALU module, clone of KCP53000 ALU check-in: 9357ad3b2f user: kc5tja tags: trunk | |
| 19:38 | capture_operands implemented check-in: 313bd82cd1 user: kc5tja tags: trunk | |
| 07:49 | Preparing to switch everything over to Wishbone B4 Pipelined. check-in: d9bfda7c63 user: kc5tja tags: trunk | |
| 07:48 | New IXU design, going back to my original ideas of how to build the thing. check-in: 2556401d8a user: kc5tja tags: trunk | |
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2019-07-16
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| 05:45 | clarify comment check-in: 8568cc35ae user: kc5tja tags: trunk | |
| 05:18 | WIP: Implement misaligned address detection, and prevent misaligned writes from generating Tilelink transactions. It's up to the FU to terminate the instruction by committing a trap to the trunk bus in a subsequent cycle. check-in: 561d833304 user: kc5tja tags: trunk | |
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2019-07-15
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| 04:47 | WIP: Implement A-channel of TileLink interface. DOES NOT YET DEAL WITH UNALIGNED ADDRESSES; instead, just ignores low-order address bits depending on size of datum being written. check-in: a783307bfd user: kc5tja tags: trunk | |
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2019-06-06
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| 07:41 | update psp check-in: daf647810c user: kc5tja tags: trunk | |
| 07:39 | Complete trunk register file source indices logic. check-in: 7170d9c66c user: kc5tja tags: trunk | |
| 07:19 | Add SUM_REQ, but I renamed it to CU_READ_VALUES. When asserted, it tells the CU when to capture the values of the register file on the trunk's register data ports. check-in: c387b96556 user: kc5tja tags: trunk | |
| 03:13 | When GO_READ is asserted by the picker, drop out of read state. check-in: 2e36a268b3 user: kc5tja tags: trunk | |
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2019-06-04
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| 15:40 | WIP: FU logic recognizes when function units broadcast results on the trunk. Keeps track of operand available status. Drives READ_REQ signal when the FU feels all operands are now ready. check-in: 87d90f5c93 user: kc5tja tags: trunk | |
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2019-06-02
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| 22:38 | initial import for FU logic check-in: 2d67e26722 user: kc5tja tags: trunk | |
| 22:34 | Relabel some of the CU signals for easier recall of who drives them check-in: e3c8c82fe7 user: kc5tja tags: trunk | |
| 06:12 | psp update check-in: 3425f3c9f4 user: kc5tja tags: trunk | |
| 05:28 | WIP! This completes the add/subtract logic for the add/store computation unit. The precise needs of the "store" logic will be dictated by how the state machine in the function unit is implemented, so I'll cross that bridge when I get there. check-in: 0c5c321cf6 user: kc5tja tags: trunk | |
| 03:16 | WIP: First CDC 6600-inspired add/store computation unit. Experimental check-in: 46868584f7 user: kc5tja tags: trunk | |
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2019-05-28
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| 01:00 | Pass I port D channel error signal through to IXU for synchronous trap processing check-in: d7b385618d user: kc5tja tags: trunk | |
| 00:44 | Remember to double-check the lowest 2 address bits check-in: d23d900a8b user: kc5tja tags: trunk | |
| 00:40 | Relabel interfaces properly; expose iq_flush check-in: f37147ffb1 user: kc5tja tags: trunk | |
| 00:27 | Jump request and ack interface check-in: 16b97e0e8b user: kc5tja tags: trunk | |
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2019-05-27
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| 22:53 | Implement o_iq_valid handshake signal. Note that it is pulsed!! (See comments in code for more details.) check-in: 2dbe6f9e6d user: kc5tja tags: trunk | |
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2019-05-26
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| 01:37 | iq_address and iq_inst_addr implemented. Confirmed proper word routing from the fetched dword. I need to double-check proper handshaking next (e.g., iq_ready and iq_valid), and after that is done, work on the control flow functionality. check-in: 23a3a9c2af user: kc5tja tags: trunk | |
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2019-05-06
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| 01:41 | Finished IFU A-channel for instruction fetch port (TileLink). check-in: e91ccded29 user: kc5tja tags: trunk | |
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2019-05-05
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| 07:51 | Makefile update to remove old ilang files check-in: e17b606295 user: kc5tja tags: trunk | |
| 07:50 | Support the byte lane select mask check-in: 33a2716e57 user: kc5tja tags: trunk | |
| 07:34 | update psp check-in: 5c7b25760b user: kc5tja tags: trunk | |
| 07:17 | WIP: Why u no work? Fails induction for unknown reasons check-in: 3a96327a8f user: kc5tja tags: trunk | |
| 03:57 | update psp check-in: 866dcdadac user: kc5tja tags: trunk | |
| 03:56 | Initial IFU code check-in: 3018838aa9 user: kc5tja tags: trunk | |
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2019-05-04
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| 15:54 | PSP update and spec update check-in: 9f51a63046 user: kc5tja tags: trunk | |
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2019-05-02
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| 22:34 | Consolidate tests into per-module tests check-in: 51b29796b7 user: kc5tja tags: trunk | |
| 22:03 | Use nmigen version of tools.py (more maintainable) check-in: 13a75afbcd user: kc5tja tags: trunk | |
| 21:53 | Migrate tests for UpCounterCSR to nmigen check-in: c8c8464c5e user: kc5tja tags: trunk | |
| 18:30 | Migrate MemCSR tests to nmigen check-in: c09510ecfd user: kc5tja tags: trunk | |
| 17:52 | Augment clean target to account for nmigen's spec_xxx directories check-in: d38e951c0e user: kc5tja tags: trunk | |
| 17:50 | Migrate InputCSR tests to nmigen check-in: 09291e359f user: kc5tja tags: trunk | |
| 17:30 | Migrate tests for ConstantCSR to nmigen check-in: c216582c93 user: kc5tja tags: trunk | |
| 05:23 | Remove dead code check-in: 138c5505a1 user: kc5tja tags: trunk | |
| 05:22 | Convert formal testbench to nmigen for CSRSelect check-in: 0e9f6538b4 user: kc5tja tags: trunk | |