Kestrel-3

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5 check-ins using file cores/dmac/rtl/verilog/dmac.sby version 02a5fc9d80

2018-10-22
01:57
Formal verification has proven itself as a viable development method. Merging into trunk. check-in: af53196bd7 user: kc5tja tags: trunk
2018-08-29
00:59
Attempt to add ROMA verification properties on my own check-in: e19f2d7e5c user: kc5tja tags: trunk
2018-08-28
21:51
Fixed the clock leak on ROMA core after adding FV to DMAC. Next step: figure out why only one bus transaction is taking place. check-in: 3ded29d7df user: kc5tja tags: trunk
21:51
Fixed the clock leak on ROMA core after adding FV to DMAC. Next step: figure out why only one bus transaction is taking place. check-in: 7756138d89 user: kc5tja tags: trunk
05:55
Remove spurious Or operator check-in: 0f3c9ade6a user: kc5tja tags: trunk