Artifact c319f1224bbf23a67a2df006bb028c7ed6c71ada1191a1c7a4a176187b1c827c:
- File cores/roma/rtl/verilog/roma.v — part of check-in [2f8acc4498] at 2018-08-29 18:44:13 on branch formal — WIP ROMA: Qualify A-channel transaction by comparing opcode. Verify that o_d_valid should be negated for as long as we lack a read result. Remove reg qualifier from all signals we "assign" to. Generate o_a_ready based on state of bits_so_far. Passes bmc; fails to prove inductively. Cause is o_d_valid && i_d_ready true while not engaged in an actual transaction. Cannot figure out how to tell prover that this is an impossible condition. (user: kc5tja size: 3462)
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