Kestrel-3

Artifact d8600c5a160ed1e3b49b43ba9bd326bb55588ffadfbb7a8697d8842bcb6cc282:

• File cores/sia/Makefile — part of check-in [1dd9f6b5cf] at 2018-11-01 17:58:44 on branch trunk — WIP: Renovate sia_tilelink.v and properties.vf to work better with Verilator. HOWEVER, Verilator now cannot locate "verilated.h" for some reason. Even if I manually include its path as a -I parameter to gcc, it refuses to find it. NOTE: I'll need to apply these kinds of renovations to all the other Verilog sources in the SIA core, and quite possibly throughout the Kestrel-3 repository as well. UUGH! I hate Verilog so much after this. The Verilog spec is total garbage if nobody is going to bother to follow it. Many thanks to ZipCPU (Dan G.) for isolating what could be one of the biggest bugs of the Kestrel-3, and a major source of what's driving me crazy with this project. (user: kc5tja size: 943)

.PHONY: test_sia_tilelink
test_sia_tilelink:
	(cd rtl/verilog/sia_tilelink && sby -f sia_tilelink.sby)

.PHONY: test_transmit_engine
test_transmit_engine:
	(cd rtl/verilog/transmit_engine && sby -f transmit_engine.sby)

.PHONY: test_receiver_engine
test_receiver_engine:
	(cd rtl/verilog/receiver_engine && sby -f receiver_engine.sby)

obj_dir: rtl/verilog/sia_tilelink/*.v rtl/verilog/receiver_engine/*.v rtl/verilog/transmit_engine/*.v rtl/verilog/sia.v bench/cpp/*.cpp
	verilator -Wall --trace -y rtl/verilog/sia_tilelink	\
	-y rtl/verilog/receiver_engine			\
	-y rtl/verilog/transmit_engine			\
	-y rtl/verilog					\
	-y ../include/verilog				\
	-CFLAGS "-I../../include/cpp"			\
	-cc sia.v					\
	--top-module sia				\
	--exe bench/cpp/sia.cpp

driver: obj_dir
	make -j -C obj_dir -f Vsia.mk Vsia

.PHONY:
verilator_test: driver
	obj_dir/Vsia

.PHONY: test
test: test_sia_tilelink test_transmit_engine test_receiver_engine verilator_test