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Overview
Artifact ID: | e6876e97e344584dc19cb9942dbdd6d473a8cc34 |
---|---|
Page Name: | Building |
Date: | 2017-09-30 16:34:04 |
Original User: | kc5tja |
Mimetype: | text/x-markdown |
Parent: | 416ad2a7e8ea57442aea442bae121b58225f05ae (diff) |
Next | 09bf5dd515658121b316680eb622e38d55ef843b |
Content
Building Kestrel 2DX
ROM image (only)
make bin/rom.bin
ROM Verilog Module
make rom
Cutting a New Version
tools/revise/revise patch to src/romver.h state src/romver.state macro ROMVER template 'Kestrel-2DX ROM {major}.{minor}.{patch}\r\n\n'
make rom
# rebuild FPGA image and test
fossil changes
fossil diff ...etc..
fossil commit
Substitute minor
or major
for patch
if appropriate.
Programming the Digilent Nexys-2 Without Affecting the Flash
Using ISE WebPack 14.7 or compatible product, you should be able to execute the following instructions with minimal issues. Of course, make sure you also have installed Digilent's proprietary programming software as well.
- Create your bit file from Xilinx ISE as you would normally; this will create a
NEXYS2.bit
file inside your ISE project directory. - Open a shell window to your project's directory containing the bit file. If your ISE project directory sits at
/tmp/fossil/kestrel-2dx/ISE/kestrel-2dx
, then you should be able to runcd /tmp/fossil/kestrel-2dx/ISE/kestrel-2dx
. - Run
sudo djtgcfg enum
. On my system, the FPGA board will have the "user name" of "Nexys2" - Run
sudo djtgcfg init -d Nexys2
. On my system, the FPGA is at JTAG index 0, and the flash for it on index 1. - Run
sudo djtgcfg prog -d Nexys2 -i 0 -f NEXYS2.bit
.
If the board is set for JTAG clocking and the project is configured to match, this will program the FPGA immediately, without affecting the flash. This is a great way to try out changes to your design without overwriting a known-good flash configuration.