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Wiki page [Building] by kc5tja 2017-09-30 16:34:04.
D 2017-09-30T16:34:04.663
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# Building Kestrel 2DX

## ROM image (only)

    make bin/rom.bin

## ROM Verilog Module

    make rom

## Cutting a New Version

    tools/revise/revise patch to src/romver.h state src/romver.state macro ROMVER template 'Kestrel-2DX ROM {major}.{minor}.{patch}\r\n\n'
    make rom
    # rebuild FPGA image and test
    fossil changes
    fossil diff ...etc..
    fossil commit

Substitute `minor` or `major` for `patch` if appropriate.

## Programming the Digilent Nexys-2 Without Affecting the Flash

Using ISE WebPack 14.7 or compatible product, you should be able to execute the following instructions with minimal issues.  Of course, make sure you also have installed Digilent's proprietary programming software as well.

1.  Create your bit file from Xilinx ISE as you would normally; this will create a `NEXYS2.bit` file inside your ISE project directory.
2.  Open a shell window to your project's directory containing the bit file.  If your ISE project directory sits at `/tmp/fossil/kestrel-2dx/ISE/kestrel-2dx`, then you should be able to run `cd /tmp/fossil/kestrel-2dx/ISE/kestrel-2dx`.
3.  Run `sudo djtgcfg enum` .  On my system, the FPGA board will have the "user name" of "Nexys2"
4.  Run `sudo djtgcfg init -d Nexys2` .  On my system, the FPGA is at JTAG index 0, and the flash for it on index 1.
5.  Run `sudo djtgcfg prog -d Nexys2 -i 0 -f NEXYS2.bit` .

If the board is set for JTAG clocking **and the project is configured to match,** this will program the FPGA immediately, without affecting the flash.  This is a great way to try out changes to your design without overwriting a known-good flash configuration.

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