According to their spec sheet:
The Propeller P2X8C4M64P (P2) is a multicore microcontroller with the performance of an MPU, excelling at real-time analog and digital applications. Designed to help engineers achieve the fastest time to market, the P2's highly flexible, deterministic hardware and development environment are free from the complication, expense and lead time associated with traditional FPGA-type development cycles.
The P2 has 8 identical 32-bit processors each with 4 KB of dual-port RAM, a configurable clock up to 320 MHz (8x160 MIPs), 64 smart I/O pins, and a common hub with 512 KB of shared RAM and a CORDIC math solver. Each of the 64 smart I/Os can be accessed by every cog, and are independently able to execute hundreds of autonomous analog and digital functions. Each Smart Pin can support almost any protocol, with a growing list of objects including 1-WIRE, CANbus, DVI, HDMI, HDTV, HUB75, HyperFlash/RAM, I²C, QSPI/QSSI, RS485, SCI/SPI, SID, SD CARD, UART/USART, USB 2.0 HOST/SLAVE, VGA, XBEE. (For R&D only; end users must seek their own protocol licenses where needed.)
External Flash or a removable SD card memory can be used to boot or store program code and data, which allows for simple product deployment, on-site updates and efficient, low-cost support.
For complete Propeller 2 specifications, documentation, development kits and boards, programming tools, developers' forum, and other community resources, visit Parallax P2 website .
Selected Specifications
- Eight 32-bit cores each with 4 KB dual-port RAM
- 512 KB shared RAM
- 64 identical Smart I/O pins
- Power core @ 1.8 VDC, I/O pins @ 3.3 VDC
- Internal ~24 MHz and ~20 kHz RC oscillators
- Low-power operation mode @ ~130 µA
- External clock input with internal loading caps
- Fractional PLL, 3 stage
- Frequency 180 MHz typical, 320 MHz extended
- Hub access speed 720 MB/s/cog @180 MHz
- Max execution @ 180 MHz 720 MIPs (90 MIPs/cog)
Hardware Function Highlights
- ADC: 64 x 14-bit
- ADC Modes: Delta-Sigma, SINC1/2/3, Scope
- Atomic Locks: 16 locks accessible by all cogs
- Comparator modes with feedback
- CORDIC math solver: 54 stage, 8 function
- Counter Modes: 28 per cog & 64-bit hub global
- Clock Modes: Six 32-bit
- DAC: 64 x 16-bit, 3 ns 75 ohm
- Debug interrupt: single-stepping & breakpoint
- Digital input filter
- Drive modes: 1.5k, 15k, 150k, 1mA, 100µA, 10µA
- Event & timer modes: 16 per cog
- Goertzel analysis: 4 ADC bit streams per cog
- Interrupts: 3 per cog, 16 event sources
- Math: SIN, LOG, TAN, ARC
- PWM: Triangle, Sawtooth, SMPS
- Quadrature Decoder
- USB 12 Mbps
- Analog Video: VGA/HDTV/NTSC/PAL
- Digital Video: HDMI 480p @60fps, 720p @24fps
- Xoroshiro128 (PRNG, noise-seeded)
Smart Pin Modes
- 64 identical Smart I/O pins, externally powered in blocks of 4
- 8-bit, 120-ohm (3 ns) and 1 k-ohm DACs with 16-bit oversampling, noise, and high/low digital modes
- Delta-sigma ADC with 5 ranges, 2 sources, and VIO/GIO calibration
- Several ADC sampling modes: automatic 2n SINC2, adjustable SINC2/SINC3, oscilloscope
- Logic, Schmitt, pin-to-pin-comparator, and 8-bit-level-comparator input modes
- 2/3/5/8-bit-unanimous input filtering with selectable sample rate
- Incorporation of inputs from relative pins, -3 to +3
- Negative or positive local feedback, with or without clocking
- Separate drive modes for high and low output: logic / 1.5 k / 15 k / 150 k / 1 mA / 100 µA / 10 µA / float
- Programmable 32-bit clock output, transition output, NCO/duty output
- Triangle/sawtooth/SMPS PWM output, 16-bit frame with 16-bit prescaler
- Quadrature decoding with 32-bit counter, both position and velocity modes
- 16 different 32-bit measurements involving one or two signals
- USB full-speed and low-speed (via odd/even pin pairs)
- Synchronous serial transmit and receive, 1 to 32 bits, up to clock/2 baud rate
- Asynchronous serial transmit and receive, 1 to 32 bits, up to clock/3 baud rate
Eight >300MHz 32-bit processors (cogs)
- Access to all I/O pins, plus four fast DAC output channels and four fast ADC input channels
- 512 longs of dual-port register RAM for code and fast variables
- 512 longs of dual-port lookup RAM for code, streamer lookup, and variables
- Ability to execute code directly from register RAM, lookup RAM, and hub RAM
- ~350 unique instructions for math, logic, timing, and control operations
- 2-clock execution for all math and logic instructions, including 16 x 16 multiply
- 6-clock custom-bytecode executor for interpreted languages
- Ability to stream hub RAM and/or lookup RAM to DACs and pins or HDMI modulator
- Ability to stream pins and/or ADCs to hub RAM
- Live colorspace conversion using a 3 x 3 matrix with 8-bit signed/unsigned coefficients
- Pixel blending instructions for 8:8:8:8 data
- 16 unique event trackers that can be polled and waited upon
- 3 prioritized interrupts that trigger on selectable events
- Hidden debug interrupt for single-stepping, breakpoint, and polling
Central hub serving the processors (cogs)
- 512 KB of contiguous RAM in a 20-bit address space
- 32-bits-per-clock sequential read/write for all cogs, simultaneously
- readable and writable as bytes, words, or longs in little-endian format
- last 16KB of RAM is write-protectable
- 32-bit, pipelined CORDIC solver with scale-factor correction
- 32-bit x 32-bit unsigned multiply with 64-bit result
- 64-bit / 32-bit unsigned divide with 32-bit quotient and 32-bit remainder
- 64-bit → 32-bit square root
- Rotate (X32,Y32) by Theta32 → (X32,Y32)
- (Rho32,Theta32) → (X32,Y32) polar-to-cartesian
- (X32,Y32) → (Rho32,Theta32) cartesian-to-polar
- 32 → 5.27 unsigned-to-logarithm
- 5.27 → 32 logarithm-to-unsigned
- Cogs can start CORDIC operations every 8 clocks and get results 55 clocks later
- 16 semaphore bits with atomic read-modify-write operations
- 64-bit free-running counter which increments every clock, cleared on reset
- High-quality pseudo-random number generator (Xoroshiro128**), true-random seeded at start-up, updates every clock, provides unique data to each cog and pin
- Mechanisms for starting, polling, and stopping cogs
- 16 KB boot ROM
- Loads into last 16 KB of hub RAM on boot-up
- SPI loader for automatic startup from 8-pin flash or SD card
- Serial loader for startup from host
- Hex and Base64 download protocols
- Terminal monitor invocable via “> ” (greater than followed by a space) and then CTRL+D
- TAQOZ Forth invocable via “> ” (greater than followed by a space) and then ESC
- Lisp console
- File management console