Index: mttroot/mtt/bin/trans/m/rbg2abg.m
==================================================================
--- mttroot/mtt/bin/trans/m/rbg2abg.m
+++ mttroot/mtt/bin/trans/m/rbg2abg.m
@@ -5,10 +5,13 @@
 % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 % %% Version control history
 % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 % %% $Id$
 % %% $Log$
+% %% Revision 1.37  1998/07/28 19:06:43  peterg
+% %% Still some bugs (vector SS ports)??
+% %%
 % %% Revision 1.36  1998/07/28 10:30:50  peterg
 % %% Implemented vector SS ports.
 % %%
 % %% Revision 1.35  1998/07/08 15:35:15  peterg
 % %% Added errorfile argument
@@ -463,13 +466,15 @@
   n_comp_bonds = length(signed_bond_list);
   direction = sign(signed_bond_list);
   
   %Find the port list for this component
   if exist([comp_type, '_cause'])==0
-    eval(['[junk1,junk2,junk3,junk4,junk5,port_list]=', comp_type, '_rbg;']);
+#    eval(['[junk1,junk2,junk3,junk4,junk5,port_list]=', comp_type, '_rbg;']);
+    eval(["ABG = ",comp_type, "_abg;"]);
+    port_list = ABG.portlist;
   else
-    port_list=comp_ports(comp_type,n_comp_bonds);
+    port_list=comp_ports(comp_type,n_comp_bonds)
   end;
 
   [n_comp_ports,m_comp_ports] = size(port_list);
   subport_list="";
   for p=1:n_comp_ports		# Expand any vector ports