Overview
Comment: | Added defaults in new form BEFORE alias expansion |
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Timelines: | family | ancestors | descendants | both | origin/master | trunk |
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SHA3-256: |
d70f8561a3371a5c596ade73b3bcedea |
User & Date: | gawthrop@users.sourceforge.net on 1998-07-02 13:28:31 |
Other Links: | branch diff | manifest | tags |
Context
1998-07-02
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13:40:50 |
Added extra ports names (due to defaults) to relevant lists: port_name port_bond check-in: e9a78e5a15 user: gawthrop@users.sourceforge.net tags: origin/master, trunk | |
13:28:31 | Added defaults in new form BEFORE alias expansion check-in: d70f8561a3 user: gawthrop@users.sourceforge.net tags: origin/master, trunk | |
12:36:39 | Initial revision check-in: 908a9986c5 user: gawthrop@users.sourceforge.net tags: origin/master, trunk | |
Changes
Modified mttroot/mtt/bin/trans/m/rbg2abg.m from [a9df87bf22] to [cdd965e19c].
1 2 3 4 5 6 7 8 9 10 11 12 13 14 | function [bonds,components] = rbg2abg(name,rbonds,rstrokes,rcomponents,port_coord,port_name,infofile) % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % %% Version control history % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % %% $Id$ % %% $Log$ % %% Revision 1.27 1998/07/02 12:24:02 peterg % %% Expand port aliases % %% % %% Revision 1.26 1998/04/16 14:07:51 peterg % %% Sorted out [] problem with vector ports -- new octave function % %% split_port % %% | > > > | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 | function [bonds,components] = rbg2abg(name,rbonds,rstrokes,rcomponents,port_coord,port_name,infofile) % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % %% Version control history % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% % %% $Id$ % %% $Log$ % %% Revision 1.28 1998/07/02 12:36:05 peterg % %% Removed debugging lines % %% % %% Revision 1.27 1998/07/02 12:24:02 peterg % %% Expand port aliases % %% % %% Revision 1.26 1998/04/16 14:07:51 peterg % %% Sorted out [] problem with vector ports -- new octave function % %% split_port % %% |
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207 208 209 210 211 212 213 | % which end of bond at component? bond_end = index(:,2); direction = -sign(bond_end-1.5*one); signed_bond_list = bond_list.*direction; components = add_bond(components,signed_bond_list',i); | > | > > > | > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > | > | | | | | | < | > | 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 | % which end of bond at component? bond_end = index(:,2); direction = -sign(bond_end-1.5*one); signed_bond_list = bond_list.*direction; components = add_bond(components,signed_bond_list',i); # Unalias all the ports on this component - if not a junction unlabelled_ports = 0; in_bonds = 0; if ((comp_type!="0")&&(comp_type!="1")) eval( ["alias = ", comp_type, '_alias';]); # Get aliases if is_struct(alias) # are there any aliases for j=1:n_comp_bonds port_name_index = getindex(port_bond,signed_bond_list(j)); port_direction = -sign(signed_bond_list(j)); if port_name_index==0 # There is no port on this bond - so try # to default unlabelled_ports++; if(unlabelled_ports==1) if port_direction>0 in_bonds++; port_name_i = "in"; else port_name_i = "out"; end; elseif (unlabelled_ports==2) if port_direction>0 if (++in_bonds>1) mtt_info(["More than one unlabelled in port on component " \ comp_name " (" comp_type ")"],fnum); else port_name_i = "in"; end else port_name_i = "out"; end; else mtt_info(["More than two unlabelled ports on component " \ comp_name " (" comp_type ")"],fnum); end mtt_info(["Defaulting to port name " port_name_i " on component " \ comp_name " (" comp_type ")" ],fnum); port_name = [port_name; ["[" port_name_i "]"]]; # add to list [port_name_index,junk] = size(port_name); # the corresponding index else port_name_i = deblank(port_name(port_name_index,:)); port_name_i = port_name_i(2:length(port_name_i)-1) # strip [] end; if struct_contains(alias,port_name_i) # Is this an alias? eval(["new_port_name_i = alias.",port_name_i]); mtt_info(["Expanding port name " port_name_i " of component " \ comp_name " (" comp_type ") to ", new_port_name_i],fnum); port_name = replace_name(port_name, \ ["[",new_port_name_i,"]"], port_name_index); end end end end; end; components % Deduce causality from the strokes (if any) and create the list of bonds causality = zeros(n_bonds,2); if n_strokes>0 |
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