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# Subsystems and Ports

EOF
}

sub output_component {
    my ($NM,$type,$cr,$arg,$rep,$stat,$connections) = @_;





	print OUT <<"EOF";
# Component $NM
  $diagram_name.subsystems.$NM.type = "$type";
  $diagram_name.subsystems.$NM.cr = "$cr";
  $diagram_name.subsystems.$NM.arg = "$arg";
  $diagram_name.subsystems.$NM.repetitions = $rep;
  $diagram_name.subsystems.$NM.status = $stat;
  $diagram_name.subsystems.$NM.connections = [$connections];
    
EOF
}

# This sort function allows components to be sorted in same order as
# label file, and alphabetically for components not in label file.
sub by_label_file {
    my ($a_index,$b_index);

    $a_index = $component_label_data{id_to_name($a)}[0];
    $b_index = $component_label_data{id_to_name($b)}[0];
    $a_index = 1e9 unless defined($a_index);
    $b_index = 1e9 unless defined($b_index);

    return ($a_index <=> $b_index) || ($a_index cmp $b_index);
}

sub output_abg {
    my ($cr,$rep,$stat,$NM,$type,$arg,$bond_id,$start,$end,@clist,$connections,$strlength);


    print_debug("WRITING OUTPUT TO STDIO...\n");
    $rep = "1";
    $stat = "-1";

    output_abg_header();
    
    foreach my $id (keys(%component_id_tag)) {
	$NM = id_to_name($id);


	$type = id_to_type($id);

	$cr = "" unless defined($cr = $component_label_data{$NM}[1]);
	$arg = "" unless defined($arg = $component_label_data{$NM}[2]);

	@clist = ();
	while (($bond_id,$start) = each(%bond_id_start_id)) {
	    push(@clist, -get_sign_of_power($bond_id) * $mtt_bond_id_index{$bond_id})
		if $start eq $id;
	}
	while (($bond_id,$end) = each(%bond_id_end_id)) {
	    
	    push(@clist, get_sign_of_power($bond_id) * $mtt_bond_id_index{$bond_id})
		if $end eq $id;

	}
	$connections = join(" ",@clist);

	output_component($NM,$type,$cr,$arg,$rep,$stat,$connections);
    }
    
    print OUT "# Ordered list of subsystem names\n";
    # order component id's so that entries found in _lbl.txt file are
    # in _lbl file order, and other entries follow.
    my (@id_list);
    @id_list = keys(%component_id_tag);







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# Subsystems and Ports

EOF
}

sub output_component {
    my ($NM,$type,$cr,$arg,$rep,$stat,$connections,$subsys_or_port) = @_;

    $_=$NM; remove_brackets(); $NM = $_;

    my $pretty_name = ($subsys_or_port eq "ports") ? "Port" : "Component";

	print OUT <<"EOF";
# $pretty_name $NM
  ${diagram_name}.${subsys_or_port}.${NM}.type = "$type";
  ${diagram_name}.${subsys_or_port}.${NM}.cr = "$cr";
  ${diagram_name}.${subsys_or_port}.${NM}.arg = "$arg";
  ${diagram_name}.${subsys_or_port}.${NM}.repetitions = $rep;
  ${diagram_name}.${subsys_or_port}.${NM}.status = $stat;
  ${diagram_name}.${subsys_or_port}.${NM}.connections = [$connections];
    
EOF
}

# This sort function allows components to be sorted in same order as
# label file, and alphabetically for components not in label file.
sub by_label_file {
    my ($a_index,$b_index);

    $a_index = $component_label_data{id_to_name($a)}[0];
    $b_index = $component_label_data{id_to_name($b)}[0];
    $a_index = 1e9 unless defined($a_index);
    $b_index = 1e9 unless defined($b_index);

    return ($a_index <=> $b_index) || ($a_index cmp $b_index);
}

sub output_abg {
    my ($cr,$rep,$stat,$NM,$type,$arg,$bond_id,$start,$end,@clist,$connections,
	$strlength,$subsys_or_port);

    print_debug("WRITING OUTPUT TO STDIO...\n");
    $rep = "1";
    $stat = "-1";

    output_abg_header();
    
    foreach my $id (keys(%component_id_tag)) {
	($subsys_or_port,$_) = id_to_name($id);
	remove_brackets(); $NM = $_;

	$type = id_to_type($id);

	$cr = "" unless defined($cr = $component_label_data{$NM}[1]);
	$arg = "" unless defined($arg = $component_label_data{$NM}[2]);

	@clist = ();
	while (($bond_id,$start) = each(%bond_id_start_id)) {
	    push(@clist, -get_sign_of_power($bond_id) * $mtt_bond_id_index{$bond_id})
		if $start eq $id;
	}
	while (($bond_id,$end) = each(%bond_id_end_id)) {
	    
	    push(@clist, get_sign_of_power($bond_id) * $mtt_bond_id_index{$bond_id})
		if $end eq $id;

	}
	$connections = join(" ",@clist);

	output_component($NM,$type,$cr,$arg,$rep,$stat,$connections,$subsys_or_port);
    }
    
    print OUT "# Ordered list of subsystem names\n";
    # order component id's so that entries found in _lbl.txt file are
    # in _lbl file order, and other entries follow.
    my (@id_list);
    @id_list = keys(%component_id_tag);
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    die " I found no text subnode of " . $node->getNodeName . "." unless
	$subnode->getNodeType == TEXT_NODE;
}

sub id_cleaner {
    s/#?([^#]*)#?/$1/;
}





sub id_to_type {
    my ( $id )= @_;
    my($type,$name);

    $_ = $component_id_tag{$id};
    id_cleaner();
    ($type, $name) = split(/:/);

    return $type;
}



sub id_to_name {
    my ( $id )= @_;
    my($type,$name);

    $_ = $component_id_tag{$id};
    id_cleaner();
    ($type, $name) = split(/:/);

    if(!defined($name)) { $name = $id };

    return $name;
}

sub print_debug {
    print STDERR $_[0] if ($debug);
}

sub usage {







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    die " I found no text subnode of " . $node->getNodeName . "." unless
	$subnode->getNodeType == TEXT_NODE;
}

sub id_cleaner {
    s/#?([^#]*)#?/$1/;
}

sub remove_brackets {
    s/^\[([^\]]*)\]$/$1/;
}

sub id_to_type {
    my ( $id )= @_;
    my($type,$name);

    $_ = $component_id_tag{$id};
    id_cleaner();
    ($type, $name) = split(/:/);

    return $type;
}

# If 1 LHS argument is used, it returns component name.  If 2 are used, it return
# "subsystem" or "port" depending on whether brackets are found in the name.
sub id_to_name {
    my ( $id )= @_;
    my($type,$name);

    $_ = $component_id_tag{$id};
    id_cleaner();
    ($type, $name) = split(/:/);

    if(!defined($name)) { $name = $id };

    return ( ($name =~ /^\[[^\]]*\]$/ ? "ports" : "subsystems" ),$name);
}

sub print_debug {
    print STDERR $_[0] if ($debug);
}

sub usage {

MTT: Model Transformation Tools
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