15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
|
sub usage;
sub read_cmp_file;
sub read_cmp_line;
sub name_anonymous_component;
sub port_or_component_or_junction;
sub read_lbl_file;
sub read_lbl_line;
sub write_header;
sub write_body;
sub strip_rubbish;
## fields to write to cmp.m
my (@component_name,
%component_type,
%component_cr,
%component_arg,
%component_rep);
my $sys = '';
GetOptions ('sys=s' => \$sys);
die usage() if ($sys eq '');
## files to read/write
my $lbl = "${sys}_lbl.txt";
my $cmp = "${sys}_cmp.txt";
my $out = "${sys}_cmp.m";
## other global variables
my (%anonymous_component_type_index);
my $debug = 1;
read_cmp_file();
read_lbl_file();
write_header();
write_body();
sub usage() {
return "Usage: lbl2cmp_txt2m --sys=<sys>\n";
}
sub read_cmp_file() {
my ($line, $name, $type, $class, $rep, $i);
my (@c_name, %c_type, %c_rep, $i_c);
my (@j_name, %j_type, %j_rep, $i_j);
my (@p_name, %p_type, %p_rep, $i_p);
$i_c = 0; # component counter
$i_j = 0; # junction counter
$i_p = 0; # port counter
open (CMP, $cmp) or die ("MTT: lbl2cmp_txt2m, cannot open $cmp");
while (<CMP>) {
chomp;
# skip blank lines
next if (/^(\s)*$/);
# skip comments
next if (/^(\s)*[%\#]/);
# remove leading and trailing whitespace
s/^\s*(\S.*\S)\s*$/$1/;
$line = $_;
print "read_cmp_file: line='${line}'\n" if defined ($debug);
($type, $name, $rep) = read_cmp_line($line);
$name = name_anonymous_component($type) if ($name eq '');
$class = port_or_component_or_junction ($type, $name);
if ($class eq "port") {
$i_p++;
$p_name[$i_p] = $name;
$p_type{$name} = $type;
$p_rep{$name} = $rep;
} elsif ($class eq "component") {
$i_c++;
$c_name[$i_c] = $name;
$c_type{$name} = $type;
$c_rep {$name} = $rep;
} elsif ($class eq "junction") {
$i_j++;
$j_name[$i_j] = $name;
$j_type{$name} = $type;
$j_rep {$name} = $rep;
} else {
die "MTT: lbl2cmp_txt2m.pl, read_cmp_file: unclassified component";
}
}
close (CMP);
$i = 0;
# assign ports (SS:[])
my $offset = 0;
while ($i < ($offset + $i_p)) {
$i++;
$name = $p_name[$i];
$component_name[$i] = $name;
$component_type{$name} = $p_type{$name};
$component_rep {$name} = $p_rep{$name};
$component_cr {$name} = '';
$component_arg {$name} = '';
}
# then assign components (including SS)
$offset = $i_p;
while ($i < ($offset + $i_c)) {
$i++;
$name = $c_name[${i}-${offset}];
$component_name[$i] = $name;
$component_type{$name} = $c_type{$name};
$component_rep {$name} = $c_rep{$name};
$component_cr {$name} = '';
$component_arg {$name} = '';
}
# then assign junctions
$offset = $i_p + $i_c;
while ($i < ($offset + $i_j)) {
$i++;
$name = $j_name[${i}-${offset}];
$component_name[$i] = $name;
$component_type{$name} = $j_type{$name};
$component_rep {$name} = $j_rep{$name};
$component_cr {$name} = '';
$component_arg {$name} = '';
}
}
sub read_cmp_line() {
my $line = $_;
my ($type, $name, $rep, $misc);
($type, $misc) = split (/:/, $line);
$type = $line unless defined ($type);
if (defined ($misc)) {
($name, $rep) = split (/\*/, $misc);
$name = $misc unless defined ($name);
}
$name = '' unless defined $name;
$rep = 1 unless defined $rep;
print "read_cmp_line: type='$type', name='$name', rep='$rep'\n" if defined ($debug);
return ($type, $name, $rep);
}
sub name_anonymous_component() {
my $type = @_;
my ($name, $num);
if (defined ($anonymous_component_type_index{$type})) {
$anonymous_component_type_index{$type}++;
} else {
$anonymous_component_type_index{$type} = 0;
}
$num = $anonymous_component_type_index{$type};
$name = "mtt${type}_${num}";
print "name_anonymous_component: type='${type}', name='${name}'\n" if defined ($debug);
return ($name);
}
sub port_or_component_or_junction() {
my ($type, $name) = @_;
my $retval;
if ($type eq "SS") {
$_ = $name;
if (/\[.+\]/) {
$retval = "port";
} else {
$retval = "component";
}
} elsif (($type eq "0") or ($type eq "1")) {
$retval = "junction";
} else {
$retval = "component";
}
print "port_or_component_or_junction: type='$type', name='$name' class='$retval'\n" if defined ($debug);
return ($retval);
}
sub read_lbl_file() {
my (@line, $name, $type, $cr, $arg, $i);
open (LBL, $lbl) or die ("MTT: lbl2cmp_txt2m, cannot open $lbl");
while (<LBL>) {
chomp;
# skip blank lines
next if (/^(\s)*$/);
# skip comments
next if (/^(\s)*[%\#]/);
# remove leading and trailing whitespace
s/^\s*(\S.*\S)\s*$/$1/;
($name, $cr, $arg) = read_lbl_line (@line);
$component_cr{$name} = $cr;
$component_arg{$name} = $arg;
}
close (LBL);
}
sub read_lbl_line() {
my @line = @_;
|
>
>
|
>
>
>
>
>
>
>
>
>
|
|
<
|
<
<
<
<
<
|
<
<
<
<
<
<
<
<
|
>
|
>
>
>
>
|
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
<
|
<
<
<
<
<
<
<
<
<
<
|
|
|
|
|
<
<
<
<
<
<
<
<
<
<
|
<
|
<
<
<
<
<
<
<
<
<
<
<
|
|
>
|
>
<
<
|
>
>
>
>
>
|
|
>
>
|
>
>
>
>
>
|
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
|
sub usage;
sub read_cmp_file;
sub read_cmp_line;
sub name_anonymous_component;
sub port_or_component_or_junction;
sub read_lbl_file;
sub read_lbl_line;
sub sort_components;
sub write_header;
sub write_body;
sub write_component;
my $debug = 0;
## fields to write to cmp.m
my (@component_name,
%component_type,
%component_cr,
%component_arg,
%component_rep);
my (@component_name_lbl_index,
%sorted_component_list,
%component_class,
%anonymous_component_type_index);
## files to read/write
my ($cmp, $lbl, $out);
my $sys = '';
GetOptions ('sys=s' => \$sys);
die usage() if ($sys eq '');
$cmp = "${sys}_cmp.txt";
$lbl = "${sys}_lbl.txt";
$out = "${sys}_cmp.m";
read_cmp_file();
read_lbl_file();
sort_components();
write_header();
write_body();
sub usage() {
return "Usage: lbl2cmp_txt2m --sys=<sys>\n";
}
sub read_cmp_file() {
my ($line, $name, $type, $class, $rep, $i);
open (CMP, $cmp) or die ("MTT: lbl2cmp_txt2m, cannot open $cmp");
$i = 0;
while (<CMP>) {
chomp;
# skip blank lines
next if (/^(\s)*$/);
# skip comments
next if (/^(\s)*[%\#]/);
# remove leading and trailing whitespace
s/^\s*(\S.*\S)\s*$/$1/;
$line = $_;
print "read_cmp_file: line='${line}'\n" if ($debug);
# cmp provides type, name and repetition information
# class is inferred from type and name
# (cr and args are placeholders)
($type, $name, $rep) = read_cmp_line($line);
$name = name_anonymous_component($type) if ($name eq '');
$class = port_or_component_or_junction ($type, $name);
$component_name [++$i] = $name;
$component_type {$name} = $type;
$component_rep {$name} = $rep;
$component_cr {$name} = '';
$component_arg {$name} = '';
$component_class {$name} = $class;
}
close (CMP);
}
sub read_cmp_line() {
my $line = $_;
my ($type, $name, $rep, $misc);
($type, $misc) = split (/:/, $line);
$type = $line unless defined ($type);
if (defined ($misc)) {
($name, $rep) = split (/\*/, $misc);
$name = $misc unless defined ($name);
}
$name = '' unless defined $name;
$rep = 1 unless defined $rep;
print "read_cmp_line: type='$type', name='$name', rep='$rep'\n" if ($debug);
return ($type, $name, $rep);
}
sub name_anonymous_component() {
my $type = @_;
my ($name, $num);
if (defined ($anonymous_component_type_index{$type})) {
$num = ++$anonymous_component_type_index{$type};
$name = "mtt${type}_${num}";
} else {
$anonymous_component_type_index{$type} = 1;
$name = "mtt${type}";
}
print "name_anonymous_component: type='${type}', name='${name}'\n" if ($debug);
return ($name);
}
sub port_or_component_or_junction() {
# ports are internal SS components (SS:[...])
# junctions are '0' and '1' types
# everything else is a component, including external SS types.
my ($type, $name) = @_;
my $retval;
if ($type eq "SS") {
$_ = $name;
if (/\[.+\]/) {
$retval = "port";
} else {
$retval = "component";
}
} elsif ($type eq "0") {
$retval = "0junction";
} elsif ($type eq "1") {
$retval = "1junction";
} else {
$retval = "component";
}
print "port_or_component_or_junction: type='$type', name='$name' class='$retval'\n" if ($debug);
return ($retval);
}
sub read_lbl_file() {
my (@line, $name, $type, $cr, $arg, $i);
open (LBL, $lbl) or die ("MTT: lbl2cmp_txt2m, cannot open $lbl");
$i = 0;
while (<LBL>) {
chomp;
# skip blank lines
next if (/^(\s)*$/);
# skip comments
next if (/^(\s)*[%\#]/);
# remove leading and trailing whitespace
s/^\s*(\S.*\S)\s*$/$1/;
# lbl provides name, cr and arg information
($name, $cr, $arg) = read_lbl_line (@line);
$component_cr{$name} = $cr;
$component_arg{$name} = $arg;
$component_name_lbl_index[++$i] = $name;
}
close (LBL);
}
sub read_lbl_line() {
my @line = @_;
|
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
|
function [comp_type, name, cr, arg, repetitions] = ${sys}_cmp(i)
EOF
close (OUT);
}
sub write_body() {
my ($name, $i);
open (OUT, ">>$out") or
die "MTT: cannot open $out for writing.\n";
$i = 0;
foreach $name (@component_name) {
if (defined ($name)) {
$i++;
print OUT
"if (i == $i)\n" .
"\tcomp_type = '$component_type{$name}';\n" .
"\tname = '$name'\n" .
"\tcr = '$component_cr{$name}';\n" .
"\targ = '$component_arg{$name}';\n" .
"\trepetitions = $component_rep{$name} ;\n" .
"end\n";
}
}
close (OUT);
}
|
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
>
|
>
>
<
<
<
<
|
|
|
|
|
|
|
|
<
<
|
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
|
function [comp_type, name, cr, arg, repetitions] = ${sys}_cmp(i)
EOF
close (OUT);
}
sub sort_components ()
{
# sorts components into the order in which they are found in the label
# file within the classes: ports, components then junctions.
my ($name, $class, $i, $j, $target);
$i = 0;
foreach $target ("port", "component", "1junction", "0junction") {
# get targets in lbl
for ($j = 1; $j < scalar @component_name_lbl_index; $j++) {
$name = $component_name_lbl_index[$j];
$class = $component_class{$name};
if ($class eq $target) {
$sorted_component_list{$name} = ++$i;
print "sorted: '$name' '$i'\n" if ($debug);
}
}
# get targets not in lbl
for ($j = 1; $j < scalar @component_name; $j++) {
$name = $component_name[$j];
$class = $component_class{$name};
if ($class eq $target) {
if (! defined ($sorted_component_list{$name})) {
$sorted_component_list{$name} = ++$i;
print "sorted: '$name' '$i'\n" if ($debug);
}
}
}
}
}
sub write_body() {
my (%reverse_sorted_component_list, $name);
%reverse_sorted_component_list = reverse (%sorted_component_list);
for (my $key = 1; $key < scalar @component_name; $key++) {
$name = $reverse_sorted_component_list{$key};
write_component ($name);
}
}
sub write_component() {
my ($name) = @_;
my $i = $sorted_component_list{$name};
open (OUT, ">>$out") or
die "MTT: cannot open $out for writing.\n";
print OUT
"if (i == $i)\n" .
"\tcomp_type = '$component_type{$name}';\n" .
"\tname = '$name'\n" .
"\tcr = '$component_cr{$name}';\n" .
"\targ = '$component_arg{$name}';\n" .
"\trepetitions = $component_rep{$name} ;\n" .
"end\n";
close (OUT);
}
|