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# Copyright (c) P.J.Gawthrop, 1996.

###############################################################
## Version control history
###############################################################
## $Id$
## $Log$



## Revision 1.26  1998/04/04 07:29:26  peterg
## SS now only port component
##
## Revision 1.25  1998/04/03 15:07:20  peterg
## Now correctly write 0/1 port names
##
## Revision 1.24  1998/04/03 14:02:50  peterg







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# Copyright (c) P.J.Gawthrop, 1996.

###############################################################
## Version control history
###############################################################
## $Id$
## $Log$
## Revision 1.27  1998/04/04 10:54:58  peterg
## Remove a debugging print statement
##
## Revision 1.26  1998/04/04 07:29:26  peterg
## SS now only port component
##
## Revision 1.25  1998/04/03 15:07:20  peterg
## Now correctly write 0/1 port names
##
## Revision 1.24  1998/04/03 14:02:50  peterg
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# Vector port definitions
  isa_PORT = ((match(str, PORT_regexp)>0) && (depth==0));

  if (isa_PORT) {
    print str
  }

# A port component is SS,0 or 1 followed by : followed by a port string
  isa_port_component = 0;
  if (match(str, delimiter)) {
    split(str,a,delimiter);
    isa_port_component = (match(a[1], port_component_regexp))&&
      (match(a[2], port_regexp)>0)
      }








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# Vector port definitions
  isa_PORT = ((match(str, PORT_regexp)>0) && (depth==0));

  if (isa_PORT) {
    print str
  }

# A port component is an SS  followed by a port string
  isa_port_component = 0;
  if (match(str, delimiter)) {
    split(str,a,delimiter);
    isa_port_component = (match(a[1], port_component_regexp))&&
      (match(a[2], port_regexp)>0)
      }

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    type = a[1];
    # Port name is the bit between the []
    port_label  = substr(a[2],2,length(a[2])-2);
    x_port[i_port_component] = x_coord;
    y_port[i_port_component] = y_coord;
    info_port[i_port_component] = fig_info();
    port_labels[i_port_component] = port_label;
    comp_type[port_label] = type;
  }

# Do the plain components
  if (isa_plain_component) {
    i_text++;

# Get repetitions (if any)
    if (match(str,repetition_regexp) > 0) {







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    type = a[1];
    # Port name is the bit between the []
    port_label  = substr(a[2],2,length(a[2])-2);
    x_port[i_port_component] = x_coord;
    y_port[i_port_component] = y_coord;
    info_port[i_port_component] = fig_info();
    port_labels[i_port_component] = port_label;

      }

# Do the plain components
  if (isa_plain_component) {
    i_text++;

# Get repetitions (if any)
    if (match(str,repetition_regexp) > 0) {
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  printf("rcomponents = [") >> b_file;
  j = 0;


# Do the port components, in order of appearance, first
  for (i = 1; i <= i_port_component; i++) {
    name = sprintf("[%s]", port_labels[i]);
    port_type = comp_type[port_labels[i]];
    cr   = "MTT_port";
    arg  = i;

    if (length(x_port[i])==0)
      printf(warning_p);
    else {
      j++;







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  printf("rcomponents = [") >> b_file;
  j = 0;


# Do the port components, in order of appearance, first
  for (i = 1; i <= i_port_component; i++) {
    name = sprintf("[%s]", port_labels[i]);
    port_type = "SS";
    cr   = "MTT_port";
    arg  = i;

    if (length(x_port[i])==0)
      printf(warning_p);
    else {
      j++;

MTT: Model Transformation Tools
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