Kestrel-3

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200 most recent check-ins tagged with "trunk"

2020-02-02
05:30
Introduce the (:remove ...) directive Leaf check-in: 3a47f2f9d6 user: kc5tja tags: trunk
01:58
Introduce (:delete ...) command to Brickie. check-in: 33dcc7213e user: kc5tja tags: trunk
2020-01-26
18:49
Introduce doc and code directives to make "weaving" easier. check-in: a28155cb66 user: kc5tja tags: trunk
16:25
Place definition of lines in appropriate context check-in: 515b6aefb4 user: kc5tja tags: trunk
2020-01-16
20:10
Introducing Brickie, a literate programming tool written for GForth, but it should be portable to DX-Forth with modest effort. It is based on Akkartik's "tangle" tool, and has similar syntax for markup. Brickie is optimized for my project's needs, however, and will evolve independently of Akkartik's work. Long story short, you write software as layers of related functionality: in a sense, you explicitly name and compose patches which ultimately leads to the finished product. This allows for code and commentary to co-reside, even when chunks of related functionality are widely separated in the source code. See http://akkartik.name/post/wart-layers for more behind the theory of this approach to literate programming. check-in: 63fa3ba241 user: kc5tja tags: trunk
2020-01-11
04:56
forgot about m4 check-in: 02c01ec8d4 user: kc5tja tags: trunk
04:50
fix formatting check-in: 77617ea1f5 user: kc5tja tags: trunk
04:42
Contribute official E3 user documentation check-in: b205b9737b user: kc5tja tags: trunk
03:54
Try to fix build bug on Ubuntu 19.04 cloud box. (This might go on for a while...) check-in: 0154dbff6a user: kc5tja tags: trunk
2020-01-09
06:11
Feature parity with E2, but much easier to add new virtual hardware. Also, much easier to support interrupts in the future as well. check-in: 7b40e899bd user: kc5tja tags: trunk
2020-01-02
23:59
Restore trunk back to pre-repkg state. check-in: 8571b9ca73 user: kc5tja tags: trunk
23:45
Remove vestiges of NRMF. check-in: db7a0e50d6 user: kc5tja tags: trunk
23:42
Replace NRMF with another non-recursive make system, purpose built. check-in: 1da36e75d2 user: kc5tja tags: trunk
05:07
Remove config.od; no longer needed. check-in: d7b42491d9 user: kc5tja tags: trunk
03:28
e3 builds, processes some basic arguments. Need to work on CPU and SIA emulation next. check-in: 456f3f082f user: kc5tja tags: trunk
00:50
Initial import of initial main.c of initial code for E3. check-in: 2d4b6522a0 user: kc5tja tags: trunk
2020-01-01
03:00
Divorce DX-Forth from processor card-specific ROM image check-in: efcd68a84e user: kc5tja tags: trunk
03:00
Oops, I forgot to link Kestrel ROM access into the address decode logic of the emulator. check-in: 5551f78da0 user: kc5tja tags: trunk
02:22
Rename rom.asm to cpurom.asm, and clean up compiler warnings check-in: 2db30aba6b user: kc5tja tags: trunk
02:05
Move origin to $40000 to prep for icoBoard Gamma FPGA bitstream check-in: 62f70e562e user: kc5tja tags: trunk
01:51
...by which I mean split apart the CPU-card functionality from the Kestrel ROM image contents. check-in: df7de75d56 user: kc5tja tags: trunk
01:50
Emulator E2 now conforms fully to E3 memory map semantics. Just need to update the DX-Forth image to exploit this. check-in: e1402a7070 user: kc5tja tags: trunk
01:40
Rename unified ROM to the "CPU ROM", the ROM which is intended to reside on the active processor card. Right now, this ROM behaves exactly as it did in the E2 emulator. However, eventually, this ROM will hold the processor's machine-mode bootstrap code and software shims for missing hardware features. check-in: 2433110035 user: kc5tja tags: trunk
2019-12-31
22:56
Upgrade to DX-Forth 1.2, which now supports the Kestrel-3/E3 memory map standards (even though the emulator doesn't quite get the firmware address decoding right yet). Fixes a number of signed vs. unsigned bugs found within DX-Forth 1.1, thanks to RAM addresses now being located in negative address space (on 32-bit machines). KNOWN BUG IN DX-FORTH 1.2: there is no way to enter an unsigned 32-bit number or unsigned 16-bit number in source form. So, HEX C000000 or HEX C000 will result in negative numbers. (This bug also existed in DX-Forth 1.1, but I wasn't aware of it.) This is an artifact of LITERAL attempting to save space in the dictionary by using the most compact numeric representation. Three workarounds exist: (1) create a parsing word which parses the next number and manually compiles a 64-bit number; (2) Wait for DX-Forth 1.3 to roll out some kind of fix for this issue; OR, (3) follow such numbers (perhaps computed from elsewhere) with explicit masks, like -65536 AND, etc. Of course, the third option is to replace DX-Forth 1.x with DX-Forth 2.x and go with native-code compilation, but this will take much longer to get working. check-in: f1c79c7f80 user: kc5tja tags: trunk
2019-12-30
17:34
Switch from old Redo-based builds back to using GNU Make (specifically using my NRMF package). check-in: da0ce0827c user: kc5tja tags: trunk
2019-12-27
19:27
Integrated the `a` assembler into the NRMF configuration. check-in: 9f4e4c255d user: kc5tja tags: trunk
17:37
Import NRMF files from Github repo check-in: 803c2a6dc9 user: kc5tja tags: trunk
2019-12-26
23:07
restoring order now? check-in: 11b423ba53 user: kc5tja tags: trunk
22:56
More testing check-in: 8182ca29ca user: kc5tja tags: trunk
22:52
testing, please disregard check-in: 8c2b8498c9 user: kc5tja tags: trunk
2019-12-21
16:36
Testing new install of fossil to see if this will preserve user credentials. check-in: aafe97f23b user: kc5tja tags: trunk
2019-11-12
05:30
Bringing REPORT up to date. Still not complete, but not entirely happy with the complexity of the firmware design either. I reserve the right to scale things way down in the next version. We shall see where this leads. check-in: 5b58b60f8a user: kc5tja tags: trunk
2019-10-27
00:52
Re-read doc; identified one code section and one whole sub-section which needs updating to the latest I/O channel model. check-in: cb2c29bfa3 user: kc5tja tags: trunk
2019-09-15
23:57
Refined some more SSP procedures. But, I am finding that complexity is growing beyond my ability to keep it in my head, and am running into limitations when it comes to distinguishing commands intended for the controller or for the units. check-in: c6e384b2d2 user: kc5tja tags: trunk
06:24
refining some of the storage protocol requirements before my laptop loses power check-in: a6c0c403cb user: kc5tja tags: trunk
2019-09-11
03:25
Simplify forth auto-load block logic check-in: 46379ac38b user: kc5tja tags: trunk
2019-09-10
05:48
I think I have completed the refinement of the boot menu logic. I feel confident I can proceed with the boot source discovery. check-in: bfb02a2af0 user: kc5tja tags: trunk
04:30
Switch methods of tracking which steps need refinement. This seems to be an easier approach, and I can track progress in an automated manner with clever use of grep. check-in: 01899c8062 user: kc5tja tags: trunk
2019-09-09
05:06
More refinements; done for this evening though. check-in: 985c171204 user: kc5tja tags: trunk
04:35
More stepwise refinements to flesh out more boot loader behavioral details, menu item structure, etc. check-in: a903a4c39f user: kc5tja tags: trunk
00:34
Missing word radically alters intended meaning of a sentence. check-in: 2c2434a794 user: kc5tja tags: trunk
2019-09-08
23:48
Bring in the project report org-mode document. Tracks stepwise refinement of system firmware, hardware design choices, etc. check-in: e485309137 user: kc5tja tags: trunk
2019-09-05
03:41
.skip and .zero support check-in: 447c21378e user: kc5tja tags: trunk
03:10
Support .asciz and fix unit test breakage in scanner check-in: f23325b630 user: kc5tja tags: trunk
02:51
.ascii support check-in: 29d317a6a2 user: kc5tja tags: trunk
2019-09-03
04:41
.8byte, .4byte, and .2byte implemented check-in: 8a46823df5 user: kc5tja tags: trunk
04:31
.half and .byte supported check-in: 4f12102c36 user: kc5tja tags: trunk
04:23
Support .word check-in: c0b13ae1bb user: kc5tja tags: trunk
02:12
Remove debugging code check-in: 233d4785af user: kc5tja tags: trunk
02:07
String expression support check-in: 88de4ec636 user: kc5tja tags: trunk
01:29
Basic .dword primitive check-in: 0dda2d09e7 user: kc5tja tags: trunk
2019-09-02
23:11
First parser integration test check-in: 9688a01a13 user: kc5tja tags: trunk
22:27
Relocate tokens beyond ASCII/UTF-8 boundaries check-in: 82629340d1 user: kc5tja tags: trunk
22:25
Unrecognized punctuation are their own symbols. check-in: 09e88c1248 user: kc5tja tags: trunk
18:24
Dead code removal check-in: f01e8709f2 user: kc5tja tags: trunk
18:19
tests for octal numbers check-in: ab025af620 user: kc5tja tags: trunk
18:15
support binary constants as well check-in: 590014a9f8 user: kc5tja tags: trunk
17:59
Numeric constants (unsigned only; parser needed for signed constants) check-in: feb73894e7 user: kc5tja tags: trunk
16:41
Remove dead code from manifest check-in: 0c54627c0d user: kc5tja tags: trunk
16:40
Remove dead code from manifest check-in: 824187d941 user: kc5tja tags: trunk
16:35
keyword check (naive implementation) check-in: e2b6e66be3 user: kc5tja tags: trunk
06:18
Track line numbers check-in: e28f0d9a4e user: kc5tja tags: trunk
05:54
Scanner grabs identifiers check-in: 1b3c87c3b9 user: kc5tja tags: trunk
04:13
Removing parser again; switching to Wirth-style recursive descent implementation check-in: d3ab39fb86 user: kc5tja tags: trunk
04:12
First scanner tests check-in: fcf8bd4e65 user: kc5tja tags: trunk
2019-08-26
06:49
Introduce failing parser test. Tried shunting yard; does not work for my needs. Must revert to recursive descent with Wirth emission. check-in: 6c6a725a22 user: kc5tja tags: trunk
2019-08-25
23:17
Forgot to include buffer migration check check-in: 651073af86 user: kc5tja tags: trunk
23:08
Make sure vector contents is preserved after expansion check-in: 0449beaa7a user: kc5tja tags: trunk
22:55
Dynamic vectors completed check-in: a52343650b user: kc5tja tags: trunk
19:16
Start on dynamic vector type. Major refactoring into smaller modules. Inconvenience from lack of shared libraries is showing. check-in: af4b7000f7 user: kc5tja tags: trunk
2019-08-24
21:28
forgot runtests check-in: de3957748f user: kc5tja tags: trunk
21:27
Remove parser; started on wrong foot. Starting over check-in: de174e1877 user: kc5tja tags: trunk
2019-08-23
06:54
Try to refactor test engine into a separate module; however, it does not work nearly as well as I would like. check-in: 0be7136182 user: kc5tja tags: trunk
2019-08-21
22:27
prepare to work on parser next check-in: ffc86e1698 user: kc5tja tags: trunk
2019-08-17
00:07
Finished (for now at least) the section abstraction. check-in: 5594d490f9 user: kc5tja tags: trunk
2019-08-16
21:38
WIP: you can emit bytes..dwords into a section now check-in: 0482ee37fa user: kc5tja tags: trunk
06:59
Start work on a next-generation assembler for the Tripos/KOS environment. Uses official RISC-V assembly language directives as much as it makes sense to. Not intended to replace gas; but I need something usable in a BCPL and Tripos environment, and gas won't be useful until it either supports hunk format executables or runs under Tripos. check-in: 431ffa1b72 user: kc5tja tags: trunk
2019-08-05
07:53
Bug fix: branch displacement was missing a bit check-in: 797fafc3c9 user: kc5tja tags: trunk
06:31
writeback logic first pass implemented. check-in: 0708c27675 user: kc5tja tags: trunk
03:44
SRLI and SRAI -- this completes OP-IMM check-in: b705e135a7 user: kc5tja tags: trunk
03:23
AND, OR, XOR check-in: 83070c8d95 user: kc5tja tags: trunk
03:21
Bug fix for SLTI: -4 < 4 would fail test check-in: 26f3c58373 user: kc5tja tags: trunk
03:02
SLTI and SLTUI check-in: fe12c3b40e user: kc5tja tags: trunk
02:49
SLLI implemented in the IXU check-in: d265210c64 user: kc5tja tags: trunk
02:30
ANDI instruction works. check-in: b0c8e8b48a user: kc5tja tags: trunk
01:20
Initial integration of ALU into IXU; no tests yet check-in: 3d81d8061e user: kc5tja tags: trunk
00:11
Simplify the ALU code significantly check-in: 84a26d5484 user: kc5tja tags: trunk
2019-08-04
21:41
Introduce (untested) ALU module, clone of KCP53000 ALU check-in: 9357ad3b2f user: kc5tja tags: trunk
19:38
capture_operands implemented check-in: 313bd82cd1 user: kc5tja tags: trunk
07:49
Preparing to switch everything over to Wishbone B4 Pipelined. check-in: d9bfda7c63 user: kc5tja tags: trunk
07:48
New IXU design, going back to my original ideas of how to build the thing. check-in: 2556401d8a user: kc5tja tags: trunk
2019-07-16
05:45
clarify comment check-in: 8568cc35ae user: kc5tja tags: trunk
05:18
WIP: Implement misaligned address detection, and prevent misaligned writes from generating Tilelink transactions. It's up to the FU to terminate the instruction by committing a trap to the trunk bus in a subsequent cycle. check-in: 561d833304 user: kc5tja tags: trunk
2019-07-15
04:47
WIP: Implement A-channel of TileLink interface. DOES NOT YET DEAL WITH UNALIGNED ADDRESSES; instead, just ignores low-order address bits depending on size of datum being written. check-in: a783307bfd user: kc5tja tags: trunk
2019-06-06
07:41
update psp check-in: daf647810c user: kc5tja tags: trunk
07:39
Complete trunk register file source indices logic. check-in: 7170d9c66c user: kc5tja tags: trunk
07:19
Add SUM_REQ, but I renamed it to CU_READ_VALUES. When asserted, it tells the CU when to capture the values of the register file on the trunk's register data ports. check-in: c387b96556 user: kc5tja tags: trunk
03:13
When GO_READ is asserted by the picker, drop out of read state. check-in: 2e36a268b3 user: kc5tja tags: trunk
2019-06-04
15:40
WIP: FU logic recognizes when function units broadcast results on the trunk. Keeps track of operand available status. Drives READ_REQ signal when the FU feels all operands are now ready. check-in: 87d90f5c93 user: kc5tja tags: trunk
2019-06-02
22:38
initial import for FU logic check-in: 2d67e26722 user: kc5tja tags: trunk
22:34
Relabel some of the CU signals for easier recall of who drives them check-in: e3c8c82fe7 user: kc5tja tags: trunk
06:12
psp update check-in: 3425f3c9f4 user: kc5tja tags: trunk
05:28
WIP! This completes the add/subtract logic for the add/store computation unit. The precise needs of the "store" logic will be dictated by how the state machine in the function unit is implemented, so I'll cross that bridge when I get there. check-in: 0c5c321cf6 user: kc5tja tags: trunk
03:16
WIP: First CDC 6600-inspired add/store computation unit. Experimental check-in: 46868584f7 user: kc5tja tags: trunk
2019-05-28
01:00
Pass I port D channel error signal through to IXU for synchronous trap processing check-in: d7b385618d user: kc5tja tags: trunk
00:44
Remember to double-check the lowest 2 address bits check-in: d23d900a8b user: kc5tja tags: trunk
00:40
Relabel interfaces properly; expose iq_flush check-in: f37147ffb1 user: kc5tja tags: trunk
00:27
Jump request and ack interface check-in: 16b97e0e8b user: kc5tja tags: trunk
2019-05-27
22:53
Implement o_iq_valid handshake signal. Note that it is pulsed!! (See comments in code for more details.) check-in: 2dbe6f9e6d user: kc5tja tags: trunk
2019-05-26
01:37
iq_address and iq_inst_addr implemented. Confirmed proper word routing from the fetched dword. I need to double-check proper handshaking next (e.g., iq_ready and iq_valid), and after that is done, work on the control flow functionality. check-in: 23a3a9c2af user: kc5tja tags: trunk
2019-05-06
01:41
Finished IFU A-channel for instruction fetch port (TileLink). check-in: e91ccded29 user: kc5tja tags: trunk
2019-05-05
07:51
Makefile update to remove old ilang files check-in: e17b606295 user: kc5tja tags: trunk
07:50
Support the byte lane select mask check-in: 33a2716e57 user: kc5tja tags: trunk
07:34
update psp check-in: 5c7b25760b user: kc5tja tags: trunk
07:20
B/c the fetch_counter was treated as an anonymous input port to the module, allowing sby to tweak its value. Very unintuitive!! check-in: af1995818c user: kc5tja tags: trunk
07:17
WIP: Why u no work? Fails induction for unknown reasons check-in: 3a96327a8f user: kc5tja tags: trunk
03:57
update psp check-in: 866dcdadac user: kc5tja tags: trunk
03:56
Initial IFU code check-in: 3018838aa9 user: kc5tja tags: trunk
2019-05-04
15:54
PSP update and spec update check-in: 9f51a63046 user: kc5tja tags: trunk
2019-05-02
22:34
Consolidate tests into per-module tests check-in: 51b29796b7 user: kc5tja tags: trunk
22:03
Use nmigen version of tools.py (more maintainable) check-in: 13a75afbcd user: kc5tja tags: trunk
21:53
Migrate tests for UpCounterCSR to nmigen check-in: c8c8464c5e user: kc5tja tags: trunk
18:30
Migrate MemCSR tests to nmigen check-in: c09510ecfd user: kc5tja tags: trunk
17:52
Augment clean target to account for nmigen's spec_xxx directories check-in: d38e951c0e user: kc5tja tags: trunk
17:50
Migrate InputCSR tests to nmigen check-in: 09291e359f user: kc5tja tags: trunk
17:30
Migrate tests for ConstantCSR to nmigen check-in: c216582c93 user: kc5tja tags: trunk
05:23
Remove dead code check-in: 138c5505a1 user: kc5tja tags: trunk
05:22
Convert formal testbench to nmigen for CSRSelect check-in: 0e9f6538b4 user: kc5tja tags: trunk
04:55
Remove Verilog-based formal test bench for MStatus check-in: a5b58db554 user: kc5tja tags: trunk
04:44
Remove from nmigen import * in favor of explicit imports check-in: 00a555b8ef user: kc5tja tags: trunk
03:21
Thank you Luke Kenneth Casson Leighton for this contribution. This shows me both where I went wrong in my previous attempts to apply nmigen towards formal verification, but also a better interface to make formal tests run automatically than through a stack of mostly-but-not-exactly-identical Makefile rules. I will start evolving the codebase to use this new approach. check-in: c2e3819404 user: kc5tja tags: trunk
2019-04-29
06:52
Updating spec and PSP check-in: d1cdbff14a user: kc5tja tags: trunk
2019-04-09
05:23
Add (M)CYCLE, (M)INSTRET check-in: 6c559135a3 user: kc5tja tags: trunk
01:16
Implement MIP register check-in: 615dbc6e78 user: kc5tja tags: trunk
2019-04-08
07:19
Complete CSRU. No I/Os to outside world yet, though, but those can be added later. From CPU's POV, all CSRs are implemented and properly handle WLRL fields. check-in: e67e2d5951 user: kc5tja tags: trunk
00:30
Remove commented old code. check-in: fcac6fca38 user: kc5tja tags: trunk
00:29
Convert MSTATUS and MIE to use MemCSR check-in: 6074d7325c user: kc5tja tags: trunk
2019-04-07
22:57
Generalize memory-only type CSRs. Some CSRs which have non-memory semantics can, in fact, use MemCSRs as a submodule, and just wrap CSR-specific logic around this. check-in: c0dba178f7 user: kc5tja tags: trunk
2019-03-25
08:15
Begin proving mstatus check-in: 1629179d84 user: kc5tja tags: trunk
06:09
Formally verify InputCSR check-in: f311559092 user: kc5tja tags: trunk
05:17
Formally verify ConstantCSR check-in: 6facb8fbe2 user: kc5tja tags: trunk
04:32
tighten CSRSelect properties check-in: d460e67f4a user: kc5tja tags: trunk
04:24
Formally prove CSRSelect check-in: f96c5158b4 user: kc5tja tags: trunk
2019-03-24
19:56
Data output logic. check-in: aa1efe0a7d user: kc5tja tags: trunk
2019-03-23
18:45
Implement MSTATUS. check-in: f226214414 user: kc5tja tags: trunk
17:37
Bringing repo up to date, as I'm giving a demo at SVFIG. check-in: e96a1d61c9 user: kc5tja tags: trunk
2019-03-18
08:25
Begin implementation of the CSR Unit. Holy heck, using nMigen for this was totally the right choice. The CSRU module is **tiny** compared to its equivalent Verilog. check-in: 4c2460e8d1 user: kc5tja tags: trunk
2019-03-16
02:45
Spec and project data updates. check-in: 2dc9dd15f4 user: kc5tja tags: trunk
2019-03-13
07:11
Beginning specification work for the KCP53000B processor design. check-in: 04d68e52a6 user: kc5tja tags: trunk
2018-11-26
18:16
SIA IS PROVEN! The core worked fine. The problem was a bug in my ROMA core instantiation. Celebration time!! check-in: 3989d347ab user: kc5tja tags: trunk
07:36
Prove in hardware that the SIA core works. IT DOES. However, there is a bug when sending bytes with relatively few bits set on the low end of the byte (e.g., 0x05 becomes 0x0A on the receiver, while 0x51 remains 0x51 on the receiver). I genuinely have no idea how or why this is happening at this time. check-in: f70ab01418 user: kc5tja tags: trunk
07:35
Parameterize the SIA core. check-in: 315211fe32 user: kc5tja tags: trunk
05:53
Fucking reset circuitry gets me every time! check-in: 8d2bf519df user: kc5tja tags: trunk
01:34
First cut at a hardware integration test for the SIA check-in: b06cdcafc5 user: kc5tja tags: trunk
2018-11-25
02:29
Forgot to remove debugging change to default loopback settings check-in: 5511953cec user: kc5tja tags: trunk
02:03
Integration test: SIA local loopback test passes! check-in: 2867a12bc1 user: kc5tja tags: trunk
02:03
Bug fix: Draw the loopback control bits from the proper data lines. check-in: 8fe7daff6e user: kc5tja tags: trunk
02:01
Bug fix: make sure loopback control bits are accounted for in formal assertions. check-in: f047e61a8d user: kc5tja tags: trunk
2018-11-01
17:58
WIP: Renovate sia_tilelink.v and properties.vf to work better with Verilator. HOWEVER, Verilator now cannot locate "verilated.h" for some reason. Even if I manually include its path as a -I parameter to gcc, it refuses to find it. NOTE: I'll need to apply these kinds of renovations to all the other Verilog sources in the SIA core, and quite possibly throughout the Kestrel-3 repository as well. UUGH! I hate Verilog so much after this. The Verilog spec is total garbage if nobody is going to bother to follow it. Many thanks to ZipCPU (Dan G.) for isolating what could be one of the biggest bugs of the Kestrel-3, and a major source of what's driving me crazy with this project. check-in: 1dd9f6b5cf user: kc5tja tags: trunk
2018-10-31
05:59
Revise TB to match structure used by ZipCPU check-in: c72d29e3e8 user: kc5tja tags: trunk
2018-10-30
17:33
Remove uncompilable code check-in: ef48c3f143 user: kc5tja tags: trunk
17:14
WIP: SIA: Passes induction but not unit tests?! WTF?! I'm getting too old for this crap. check-in: 857710bfcf user: kc5tja tags: trunk
2018-10-26
18:47
SIA: Adjust working paths check-in: 74a8631b27 user: kc5tja tags: trunk
18:40
Remove unnecessary subdirectories check-in: 3d2b8fb5b2 user: kc5tja tags: trunk
18:39
WIP: SIA: Clean up directory structure check-in: 9605232766 user: kc5tja tags: trunk
18:17
WIP: SIA: First unit test for SIA check-in: eda0bdb81a user: kc5tja tags: trunk
16:22
WIP: SIA: Top-level check-in: caf59227ca user: kc5tja tags: trunk
06:51
SIA: Transmit engine seems to be complete. Next step: top-level. Again. check-in: ea401e4d06 user: kc5tja tags: trunk
06:24
WIP: SIA: Integrate transmit engine baud rate generator. Having the BRG as a separate module made the top-level unnecessarily complex, as some signal wires were just not used, and others just not needed. Does not yet pass formal. check-in: d1e65629f7 user: kc5tja tags: trunk
2018-10-22
02:18
SIA: Why didn't the merge include the makefile? check-in: 40bc0dad6e user: kc5tja tags: trunk
02:09
Import roma core from formal branch check-in: f6bd84d868 user: kc5tja tags: trunk
02:03
Merging did the wrong thing with the DMAC. Bring in the latest DMAC. check-in: 16aceea475 user: kc5tja tags: trunk
01:57
Formal verification has proven itself as a viable development method. Merging into trunk. check-in: af53196bd7 user: kc5tja tags: trunk
2018-08-29
00:59
Attempt to add ROMA verification properties on my own check-in: e19f2d7e5c user: kc5tja tags: trunk
2018-08-28
21:51
Fixed the clock leak on ROMA core after adding FV to DMAC. Next step: figure out why only one bus transaction is taking place. check-in: 3ded29d7df user: kc5tja tags: trunk
21:51
Fixed the clock leak on ROMA core after adding FV to DMAC. Next step: figure out why only one bus transaction is taking place. check-in: 7756138d89 user: kc5tja tags: trunk
05:55
Remove spurious Or operator check-in: 0f3c9ade6a user: kc5tja tags: trunk
05:42
Make unit test pass for DMAC check-in: f2a9d73ac1 user: kc5tja tags: trunk
04:40
Fix commentary check-in: eaace617c1 user: kc5tja tags: trunk
04:36
Introduce some formal verification for the DMAC check-in: db46c3c0e7 user: kc5tja tags: trunk
01:19
ROMA + DMAC = working now, due to DDR clock buffer. check-in: 2795fa984f user: kc5tja tags: trunk
2018-08-25
02:34
ROMA: Fix data alignment bug. check-in: 1d81dbc235 user: kc5tja tags: trunk
00:20
Fix integration test MOSI/MISO assignment check-in: a79aca60ee user: kc5tja tags: trunk
2018-08-24
05:33
WIP: FPGA programs OK; flash programs OK; DMAC seems to be working OK; ROMA seems to be working OK; however, data read back is always $FF on the LEDs. This suggests either the CPLD is interfering with my communications somehow, OR, I'm botching the SPI protocol somehow. Unsure which yet. More research is needed. check-in: ed4beeb135 user: kc5tja tags: trunk
00:59
Refactor common definitions into shared headers check-in: 3444a010e1 user: kc5tja tags: trunk
2018-08-23
23:51
ROMA: Support back-to-back transactions check-in: d3867aab51 user: kc5tja tags: trunk
23:29
ROMA: Forgot to drive the CLK output check-in: f7064f5df0 user: kc5tja tags: trunk
23:25
ROMA: I think it is finished. check-in: 2bccfe58ef user: kc5tja tags: trunk
23:10
Confirm proper data output check-in: 85e9538b39 user: kc5tja tags: trunk
22:48
ROMA: Proper D-channel handoff check-in: 1181e5b5d7 user: kc5tja tags: trunk
22:43
Negate SPI Flash CS after 64 data bits read check-in: e4574d60c9 user: kc5tja tags: trunk
07:36
ROMA: Send 21-bit dword-aligned address too check-in: a777854d78 user: kc5tja tags: trunk
07:20
ROMA: Send command byte on read request check-in: cffa191f94 user: kc5tja tags: trunk
07:00
ROMA: Recognize read request check-in: 0892ceaf82 user: kc5tja tags: trunk
06:02
ROMA: Slave A-channel first commit check-in: 768fc08020 user: kc5tja tags: trunk
05:48
First commit for ROMA core. check-in: e4318b055e user: kc5tja tags: trunk
2018-08-17
19:47
WIP: Trying to get E2 to build in new environment check-in: c47448ac7d user: kc5tja tags: trunk
17:44
DXForth source tree check-in: fe4ca6880a user: kc5tja tags: trunk
17:39
DXForth binary generation check-in: 711ad764bd user: kc5tja tags: trunk
17:38
Include path support for more sophisticated software builds. check-in: f76a09e9d5 user: kc5tja tags: trunk