Kestrel-3

Check-in [f70ab01418]
Login

Many hyperlinks are disabled.
Use anonymous login to enable hyperlinks.

Overview
Comment:Prove in hardware that the SIA core works. IT DOES. However, there is a bug when sending bytes with relatively few bits set on the low end of the byte (e.g., 0x05 becomes 0x0A on the receiver, while 0x51 remains 0x51 on the receiver). I genuinely have no idea how or why this is happening at this time.
Downloads: Tarball | ZIP archive | SQL archive
Timelines: family | ancestors | descendants | both | trunk
Files: files | file ages | folders
SHA3-256:f70ab01418c5c80a2c140f103f541b980cb50450c615400f9c96319bc5dd0785
User & Date: kc5tja 2018-11-26 07:36:40
Context
2018-11-26
18:16
SIA IS PROVEN! The core worked fine. The problem was a bug in my ROMA core instantiation. Celebration time!! check-in: 3989d347ab user: kc5tja tags: trunk
07:36
Prove in hardware that the SIA core works. IT DOES. However, there is a bug when sending bytes with relatively few bits set on the low end of the byte (e.g., 0x05 becomes 0x0A on the receiver, while 0x51 remains 0x51 on the receiver). I genuinely have no idea how or why this is happening at this time. check-in: f70ab01418 user: kc5tja tags: trunk
07:35
Parameterize the SIA core. check-in: 315211fe32 user: kc5tja tags: trunk
Changes
Hide Diffs Unified Diffs Ignore Whitespace Patch

Changes to cores/step-2-dmac-roma-sia-test/icoboard.pcf.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17






set_io --warn-no-port i_clk_100MHz R9
set_io --warn-no-port i_reset      K11
set_io --warn-no-port o_txd        C8

set_io --warn-no-port o_spi_mosi P12
set_io --warn-no-port i_spi_miso P11
set_io --warn-no-port o_spi_clk	 R11
set_io --warn-no-port o_spi_cs_n R12

set_io --warn-no-port o_pmod1_1  D8
set_io --warn-no-port o_pmod1_2  B9
set_io --warn-no-port o_pmod1_3  B10
set_io --warn-no-port o_pmod1_4  B11
set_io --warn-no-port o_pmod1_7  B8
set_io --warn-no-port o_pmod1_8  A9
set_io --warn-no-port o_pmod1_9  A10
set_io --warn-no-port o_pmod1_10 A11












|










>
>
>
>
>
>
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
set_io --warn-no-port i_clk_100MHz R9
set_io --warn-no-port i_reset      K11
set_io --warn-no-port o_txd        C8

set_io --warn-no-port o_spi_mosi P12
set_io --warn-no-port i_spi_miso P11
set_io --warn-no-port o_spi_clk  R11
set_io --warn-no-port o_spi_cs_n R12

set_io --warn-no-port o_pmod1_1  D8
set_io --warn-no-port o_pmod1_2  B9
set_io --warn-no-port o_pmod1_3  B10
set_io --warn-no-port o_pmod1_4  B11
set_io --warn-no-port o_pmod1_7  B8
set_io --warn-no-port o_pmod1_8  A9
set_io --warn-no-port o_pmod1_9  A10
set_io --warn-no-port o_pmod1_10 A11

set_io --warn-no-port i_cts2    B4
set_io --warn-no-port o_txd2    A2
set_io --warn-no-port i_rxd2    C3
set_io --warn-no-port o_rts2    A5

Changes to cores/step-2-dmac-roma-sia-test/roma-sia-test.v.

16
17
18
19
20
21
22





23
24
25
26
27
28
29
..
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
...
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128








129
130
131
132
133
134
135
...
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
...
233
234
235
236
237
238
239











240
241
242
243
244
245
246
247
	o_pmod1_8,
	o_pmod1_9,
	o_pmod1_10,

	// Serial Interface (to PC)

	o_txd,






	// Flash ROM interface

	o_spi_mosi,
	i_spi_miso,
	o_spi_clk,
	o_spi_cs_n
................................................................................
	wire increment_read_pointer;
	wire issue_rom_read;

	reg [23:0] read_pointer;

	always @(posedge clk_50MHz) begin
		if(i_reset) begin
			read_pointer <= 24'h100000;	// Start at 1MB mark
		end
		else if(increment_read_pointer) begin
			read_pointer <= read_pointer + 1;
		end
	end

	// Here's where we drive the ROMA's private A-channel with the
	// RP register.

	wire [2:0] roma_a_opcode;
        assign roma_a_opcode = `A_OPC_GET;
	wire [20:0] roma_a_address; // actually a word address!
	assign roma_a_address = read_pointer[23:3];
	reg roma_a_valid;
	wire roma_a_ready;

	always @(posedge clk_50MHz) begin
		roma_a_valid <= 0;

		if(issue_rom_read) begin
................................................................................
		fetched_byte <= fetched_byte;
		roma_d_ready <= 0;

		if(read_rom_byte) begin
			roma_d_ready <= 1;
			if(roma_d_valid) begin
				case(read_pointer[2:0])
				0: fetched_byte <= roma_d_data[7:0];
				1: fetched_byte <= roma_d_data[15:8];
				2: fetched_byte <= roma_d_data[23:16];
				3: fetched_byte <= roma_d_data[31:23];
				4: fetched_byte <= roma_d_data[39:32];
				5: fetched_byte <= roma_d_data[47:40];
				6: fetched_byte <= roma_d_data[55:48];
				7: fetched_byte <= roma_d_data[63:56];








				endcase
			end
		end
	end

	// When writing to the SIA, we always write to the TXOUT
	// register.  Everything else is assumed to be default.
................................................................................
	wire increment_read_pointer;
	wire read_rom_byte;
	wire issue_sia_write;
	wire wait_sia_ack;
	wire goto_1;

        assign issue_rom_read = (state == 1);
	assign increment_read_pointer = (state == 2);
	assign read_rom_byte = (state == 2);
	assign issue_sia_write = (state == 3);
	assign wait_sia_ack = (state == 4);
	assign goto_1 = (state == 0) || (state == 5) || (state == 6) || (state == 7);

	// The ROMA core interfaces to the flash ROM on the icoBoard Gamma.

................................................................................

	assign o_spi_cs_n = ~flash_cs;

	// The SIA core interfaces to the host PC.

	output wire o_txd;












	sia SIA(
		.i_clk(clk_50MHz),
		.i_reset(i_reset),

		.i_a_opcode(`A_OPC_PUT_FULL),
		.i_a_source(2'd0),
		.i_a_size(`A_SIZ_BYTE),
		.i_a_mask(8'h01),







>
>
>
>
>







 







|












|







 







|
|
|
|
|
|
|
|
>
>
>
>
>
>
>
>







 







|







 







>
>
>
>
>
>
>
>
>
>
>
|







16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
..
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
...
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
...
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
...
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
	o_pmod1_8,
	o_pmod1_9,
	o_pmod1_10,

	// Serial Interface (to PC)

	o_txd,

	i_cts2,
	o_txd2,
	i_rxd2,
	o_rts2,

	// Flash ROM interface

	o_spi_mosi,
	i_spi_miso,
	o_spi_clk,
	o_spi_cs_n
................................................................................
	wire increment_read_pointer;
	wire issue_rom_read;

	reg [23:0] read_pointer;

	always @(posedge clk_50MHz) begin
		if(i_reset) begin
			read_pointer <= 24'h000000;	// Start at 1MB mark
		end
		else if(increment_read_pointer) begin
			read_pointer <= read_pointer + 1;
		end
	end

	// Here's where we drive the ROMA's private A-channel with the
	// RP register.

	wire [2:0] roma_a_opcode;
        assign roma_a_opcode = `A_OPC_GET;
	wire [20:0] roma_a_address; // actually a word address!
	assign roma_a_address = {read_pointer[23:3], 3'b000};
	reg roma_a_valid;
	wire roma_a_ready;

	always @(posedge clk_50MHz) begin
		roma_a_valid <= 0;

		if(issue_rom_read) begin
................................................................................
		fetched_byte <= fetched_byte;
		roma_d_ready <= 0;

		if(read_rom_byte) begin
			roma_d_ready <= 1;
			if(roma_d_valid) begin
				case(read_pointer[2:0])
				3'd0: fetched_byte <= roma_d_data[7:0];
				3'd1: fetched_byte <= roma_d_data[15:8];
				3'd2: fetched_byte <= roma_d_data[23:16];
				3'd3: fetched_byte <= roma_d_data[31:23];
				3'd4: fetched_byte <= roma_d_data[39:32];
				3'd5: fetched_byte <= roma_d_data[47:40];
				3'd6: fetched_byte <= roma_d_data[55:48];
				3'd7: fetched_byte <= roma_d_data[63:56];
//				3'd0: fetched_byte <= 8'h11;
//				3'd1: fetched_byte <= 8'h22;
//				3'd2: fetched_byte <= 8'h33;
//				3'd3: fetched_byte <= 8'h44;
//				3'd4: fetched_byte <= 8'h55;
//				3'd5: fetched_byte <= 8'h66;
//				3'd6: fetched_byte <= 8'h77;
//				3'd7: fetched_byte <= 8'h88;
				endcase
			end
		end
	end

	// When writing to the SIA, we always write to the TXOUT
	// register.  Everything else is assumed to be default.
................................................................................
	wire increment_read_pointer;
	wire read_rom_byte;
	wire issue_sia_write;
	wire wait_sia_ack;
	wire goto_1;

        assign issue_rom_read = (state == 1);
	assign increment_read_pointer = (state == 5);
	assign read_rom_byte = (state == 2);
	assign issue_sia_write = (state == 3);
	assign wait_sia_ack = (state == 4);
	assign goto_1 = (state == 0) || (state == 5) || (state == 6) || (state == 7);

	// The ROMA core interfaces to the flash ROM on the icoBoard Gamma.

................................................................................

	assign o_spi_cs_n = ~flash_cs;

	// The SIA core interfaces to the host PC.

	output wire o_txd;

	input wire i_cts2;
	output wire o_txd2;
	input wire i_rxd2;
	output wire o_rts2;

	assign o_txd2 = o_txd;
	assign o_rts2 = 0;

	sia #(
		.DEFAULT_DIVISOR(20'd5208)
	)
	SIA(
		.i_clk(clk_50MHz),
		.i_reset(i_reset),

		.i_a_opcode(`A_OPC_PUT_FULL),
		.i_a_source(2'd0),
		.i_a_size(`A_SIZ_BYTE),
		.i_a_mask(8'h01),