Kestrel-3

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Overview
Comment:Bug fix: make sure loopback control bits are accounted for in formal assertions.
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SHA3-256:f047e61a8d40fd440bd809d5250aed0abdafbee2a1beeee0081d791bd79f9423
User & Date: kc5tja 2018-11-25 02:01:07
Context
2018-11-25
02:03
Bug fix: Draw the loopback control bits from the proper data lines. check-in: 8fe7daff6e user: kc5tja tags: trunk
02:01
Bug fix: make sure loopback control bits are accounted for in formal assertions. check-in: f047e61a8d user: kc5tja tags: trunk
2018-11-01
17:58
WIP: Renovate sia_tilelink.v and properties.vf to work better with Verilator. HOWEVER, Verilator now cannot locate "verilated.h" for some reason. Even if I manually include its path as a -I parameter to gcc, it refuses to find it. NOTE: I'll need to apply these kinds of renovations to all the other Verilog sources in the SIA core, and quite possibly throughout the Kestrel-3 repository as well. UUGH! I hate Verilog so much after this. The Verilog spec is total garbage if nobody is going to bother to follow it. Many thanks to ZipCPU (Dan G.) for isolating what could be one of the biggest bugs of the Kestrel-3, and a major source of what's driving me crazy with this project. check-in: 1dd9f6b5cf user: kc5tja tags: trunk
Changes
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Changes to cores/sia/rtl/verilog/sia_tilelink/properties.vf.

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// When writing the BAUD register, we must accept the data that comes in on
// the data bus, guarded by the i_a_mask bits (one per byte lane).
//
// Remember that BAUD is a 32-bit register, of which only 20 bits are valid.
// Writes to the upper-most byte are presently ignored.












always @(posedge i_clk)
if(&{
	f_past_valid,
	$stable(i_reset) && !i_reset,
	$past(wr_baud),
	$past(i_a_mask[6])







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// When writing the BAUD register, we must accept the data that comes in on
// the data bus, guarded by the i_a_mask bits (one per byte lane).
//
// Remember that BAUD is a 32-bit register, of which only 20 bits are valid.
// The uppermost byte controls the loopback settings.

always @(posedge i_clk)
if(&{
	f_past_valid,
	$stable(i_reset) && !i_reset,
	$past(wr_baud),
	$past(i_a_mask[7])
}) begin
	assert(o_txd_loopback == $past(i_a_data[63:62]));
	assert(o_rxd_loopback == $past(i_a_data[61]));
end

always @(posedge i_clk)
if(&{
	f_past_valid,
	$stable(i_reset) && !i_reset,
	$past(wr_baud),
	$past(i_a_mask[6])