Kestrel-3

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Overview
Comment:Bug fix: Draw the loopback control bits from the proper data lines.
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SHA3-256:8fe7daff6ec8e313c53cbdf5c9c07dba967576056a186626e79e26c2af1b97e4
User & Date: kc5tja 2018-11-25 02:03:11
Context
2018-11-25
02:03
Integration test: SIA local loopback test passes! check-in: 2867a12bc1 user: kc5tja tags: trunk
02:03
Bug fix: Draw the loopback control bits from the proper data lines. check-in: 8fe7daff6e user: kc5tja tags: trunk
02:01
Bug fix: make sure loopback control bits are accounted for in formal assertions. check-in: f047e61a8d user: kc5tja tags: trunk
Changes
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Changes to cores/sia/rtl/verilog/sia_tilelink/sia_tilelink.v.

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		end
	end

	// The SIA is a configurable UART.  You are free to set
	// the data rate via the BAUD register.  See the Kestrel-3
	// wiki for details on how to calculate the value.
	wire wr_baud = is_put & addr_baud;


	output wire [19:0] o_divisor;
	assign o_divisor = r_baud;
	reg [19:0] r_baud;


	output wire [1:0] o_txd_loopback;
	assign o_txd_loopback = r_txd_loopback;

	reg [1:0] r_txd_loopback;
	output wire o_rxd_loopback;
	assign o_rxd_loopback = r_rxd_loopback;
	reg r_rxd_loopback;

	always @(posedge i_clk) begin
		r_baud <= r_baud;
		r_txd_loopback <= r_txd_loopback;
		r_rxd_loopback <= r_rxd_loopback;

		if(i_reset) begin
			r_baud <= 20'd10415;


		end
		else if(wr_baud) begin
			if(i_a_mask[7]) begin
				r_txd_loopback <= i_a_data[31:30];
				r_rxd_loopback <= i_a_data[29];
			end
			if(i_a_mask[6]) r_baud[19:16] <= i_a_data[51:48];
			if(i_a_mask[5]) r_baud[15:8] <= i_a_data[47:40];
			if(i_a_mask[4]) r_baud[7:0] <= i_a_data[39:32];
		end
	end








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		end
	end

	// The SIA is a configurable UART.  You are free to set
	// the data rate via the BAUD register.  See the Kestrel-3
	// wiki for details on how to calculate the value.
	wire wr_baud = is_put & addr_baud;

	reg [19:0] r_baud;
	output wire [19:0] o_divisor;
	assign o_divisor = r_baud;


	reg [1:0] r_txd_loopback;
	output wire [1:0] o_txd_loopback;
	assign o_txd_loopback = r_txd_loopback;

	reg r_rxd_loopback;
	output wire o_rxd_loopback;
	assign o_rxd_loopback = r_rxd_loopback;


	always @(posedge i_clk) begin
		r_baud <= r_baud;
		r_txd_loopback <= r_txd_loopback;
		r_rxd_loopback <= r_rxd_loopback;

		if(i_reset) begin
			r_baud <= 20'd10415;
			r_txd_loopback <= 0;
			r_rxd_loopback <= 1;
		end
		else if(wr_baud) begin
			if(i_a_mask[7]) begin
				r_txd_loopback <= i_a_data[63:62];
				r_rxd_loopback <= i_a_data[61];
			end
			if(i_a_mask[6]) r_baud[19:16] <= i_a_data[51:48];
			if(i_a_mask[5]) r_baud[15:8] <= i_a_data[47:40];
			if(i_a_mask[4]) r_baud[7:0] <= i_a_data[39:32];
		end
	end