Kestrel-3

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Comment:Fucking reset circuitry gets me every time!
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SHA3-256:8d2bf519df33cddb1268d12445f6b08caeb34288d4cf6a201baeb3abec65d231
User & Date: kc5tja 2018-11-26 05:53:04
Context
2018-11-26
07:35
Parameterize the SIA core. check-in: 315211fe32 user: kc5tja tags: trunk
05:53
Fucking reset circuitry gets me every time! check-in: 8d2bf519df user: kc5tja tags: trunk
01:34
First cut at a hardware integration test for the SIA check-in: b06cdcafc5 user: kc5tja tags: trunk
Changes
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Changes to cores/step-2-dmac-roma-sia-test/icoboard.pcf.

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set_io --warn-no-port i_reset      K11
set_io --warn-no-port o_txd        C8

set_io --warn-no-port o_spi_mosi P12
set_io --warn-no-port i_spi_miso P11
set_io --warn-no-port o_spi_clk	 R11
set_io --warn-no-port o_spi_cs_n R12
















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set_io --warn-no-port i_reset      K11
set_io --warn-no-port o_txd        C8

set_io --warn-no-port o_spi_mosi P12
set_io --warn-no-port i_spi_miso P11
set_io --warn-no-port o_spi_clk	 R11
set_io --warn-no-port o_spi_cs_n R12

set_io --warn-no-port o_pmod1_1  D8
set_io --warn-no-port o_pmod1_2  B9
set_io --warn-no-port o_pmod1_3  B10
set_io --warn-no-port o_pmod1_4  B11
set_io --warn-no-port o_pmod1_7  B8
set_io --warn-no-port o_pmod1_8  A9
set_io --warn-no-port o_pmod1_9  A10
set_io --warn-no-port o_pmod1_10 A11

Changes to cores/step-2-dmac-roma-sia-test/roma-sia-test.v.

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`default_nettype none

`include "tilelink.vh"

module top (
	i_clk_100MHz,
	i_reset,












	// Serial Interface (to PC)

	o_txd,

	// Flash ROM interface

	o_spi_mosi,
	i_spi_miso,
	o_spi_clk,
	o_spi_cs_n
);
	input wire i_reset;



























	// The ROMA cannot be driven any faster than 50MHz.  Therefore,
	// we drive the whole system at 50MHz just to keep things simple.

	input wire i_clk_100MHz;
	reg clk_50MHz;

	always @(posedge i_clk_100MHz) begin
		clk_50MHz <= clk_50MHz;

		if(i_reset) begin
			clk_50MHz <= 0;
		end
		else begin
			clk_50MHz <= ~clk_50MHz;
		end
	end

	// Here's our make-shift DMA controller.
	//
	// The RP register (Read Pointer) is a 24-bit address counter.
	// It's used to read through the flash ROM byte by byte.
	
................................................................................
			read_pointer <= read_pointer + 1;
		end
	end

	// Here's where we drive the ROMA's private A-channel with the
	// RP register.

	wire [2:0] roma_a_opcode = `A_OPC_GET;

	wire [20:0] roma_a_address; // actually a word address!
	assign roma_a_address = read_pointer[23:3];
	reg roma_a_valid;
	wire roma_a_ready;

	always @(posedge clk_50MHz) begin
		roma_a_valid <= 0;
................................................................................

	always @(posedge clk_50MHz) begin
		state <= state;

		if(i_reset) begin
			state <= 0;
		end

		else if(goto_1) begin
			state <= 1;
		end
		else if(issue_rom_read && roma_a_ready) begin
			state <= 2;
		end
		else if(read_rom_byte && roma_d_valid) begin
			state <= 3;
		end
		else if(issue_sia_write && sia_a_ready) begin
			state <= 4;
		end
		else if(wait_sia_ack && sia_d_valid) begin
			state <= 5;
		end
		else begin
			state <= 1;
		end
	end

	wire issue_rom_read;
	wire increment_read_pointer;
	wire read_rom_byte;
	wire issue_sia_write;
................................................................................
	wire goto_1;

        assign issue_rom_read = (state == 1);
	assign increment_read_pointer = (state == 2);
	assign read_rom_byte = (state == 2);
	assign issue_sia_write = (state == 3);
	assign wait_sia_ack = (state == 4);
	assign goto_1 = (state == 5);

	// The ROMA core interfaces to the flash ROM on the icoBoard Gamma.

	wire flash_clk;
	wire flash_cs;

	output wire o_spi_mosi;







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`default_nettype none

`include "tilelink.vh"

module top (
	i_clk_100MHz,
	i_reset,

	// Diagnostics

	o_pmod1_1,
	o_pmod1_2,
	o_pmod1_3,
	o_pmod1_4,
	o_pmod1_7,
	o_pmod1_8,
	o_pmod1_9,
	o_pmod1_10,

	// Serial Interface (to PC)

	o_txd,

	// Flash ROM interface

	o_spi_mosi,
	i_spi_miso,
	o_spi_clk,
	o_spi_cs_n
);
	input wire i_reset;

	output wire o_pmod1_1;
	output wire o_pmod1_2;
	output wire o_pmod1_3;
	output wire o_pmod1_4;
	output wire o_pmod1_7;
	output wire o_pmod1_8;
	output wire o_pmod1_9;
	output wire o_pmod1_10;

	wire [7:0] leds;
	assign {
		o_pmod1_1, o_pmod1_7, o_pmod1_2, o_pmod1_8,
		o_pmod1_3, o_pmod1_9, o_pmod1_4, o_pmod1_10
	} = leds;

	assign leds = {
		issue_rom_read,
		read_rom_byte,
		issue_sia_write,
		wait_sia_ack,
		clk_50MHz,
		roma_a_valid,
		roma_a_ready,
		roma_d_valid
	};

	// The ROMA cannot be driven any faster than 50MHz.  Therefore,
	// we drive the whole system at 50MHz just to keep things simple.

	input wire i_clk_100MHz;
	reg clk_50MHz;

	always @(posedge i_clk_100MHz) begin






		clk_50MHz <= ~clk_50MHz;

	end

	// Here's our make-shift DMA controller.
	//
	// The RP register (Read Pointer) is a 24-bit address counter.
	// It's used to read through the flash ROM byte by byte.
	
................................................................................
			read_pointer <= read_pointer + 1;
		end
	end

	// Here's where we drive the ROMA's private A-channel with the
	// RP register.

	wire [2:0] roma_a_opcode;
        assign roma_a_opcode = `A_OPC_GET;
	wire [20:0] roma_a_address; // actually a word address!
	assign roma_a_address = read_pointer[23:3];
	reg roma_a_valid;
	wire roma_a_ready;

	always @(posedge clk_50MHz) begin
		roma_a_valid <= 0;
................................................................................

	always @(posedge clk_50MHz) begin
		state <= state;

		if(i_reset) begin
			state <= 0;
		end
		else begin
			if(goto_1) begin
				state <= 1;
			end
			else if(issue_rom_read && roma_a_ready) begin
				state <= 2;
			end
			else if(read_rom_byte && roma_d_valid) begin
				state <= 3;
			end
			else if(issue_sia_write && sia_a_ready) begin
				state <= 4;
			end
			else if(wait_sia_ack && sia_d_valid) begin
				state <= 5;
			end


		end
	end

	wire issue_rom_read;
	wire increment_read_pointer;
	wire read_rom_byte;
	wire issue_sia_write;
................................................................................
	wire goto_1;

        assign issue_rom_read = (state == 1);
	assign increment_read_pointer = (state == 2);
	assign read_rom_byte = (state == 2);
	assign issue_sia_write = (state == 3);
	assign wait_sia_ack = (state == 4);
	assign goto_1 = (state == 0) || (state == 5) || (state == 6) || (state == 7);

	// The ROMA core interfaces to the flash ROM on the icoBoard Gamma.

	wire flash_clk;
	wire flash_cs;

	output wire o_spi_mosi;