Update of "Development Strategy"

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Artifact ID: 427d3673281d6ea269bcfbd3a38db2b766b76244a483843daf7dce754b44a739
Page Name:Development Strategy
Date: 2018-01-21 00:57:29
Original User: kc5tja
  1. Port the GPIA core to run natively on a TileLink TL-UL interconnect.
  2. Develop the remote-side logic for a ByteLink interconnect. This will let me send read/write byte/half-word/word/double-word requests from the Kestrel-2DX to see if the GPIA is working. This will serve as a surrogate for the final CPU design that I intend.
  3. Make sure I can toggle LEDs using the debug port interactively from the Kestrel-2DX.
  4. Port my Serial Interface Adapter to the Kestrel-3.
  5. Interactively confirm that the serial link works on the Kestrel-3 in loop-back mode.
  6. Develop final SRAM interface.
  7. Make sure I can perform basic RAM tests interactively from the Kestrel-2DX.
  8. Develop a "ROM" system using block RAMs. (from CPU's perspective, it's ROM; from the ByteLink interface, it's RAM.)
  9. Make sure I can write to and read back from the "ROM" interactively from the Kestrel-2DX.
  10. Port the KCP53000 to run on the new platform. Fix perf regressions. Use TileLink front-side bus.
  11. Write first-boot firmware that writes "Hello world" to the SIA or something. Upload it from the Kestrel-2DX.
  12. Boot the Kestrel-3 for the first time, and hope for the best.