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Overview
Comment:SIA IS PROVEN! The core worked fine. The problem was a bug in my ROMA core instantiation. Celebration time!!
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SHA3-256:3989d347ab6d85cc7ecfe47883cad693fa5b76225141a67845430de42d0fb14c
User & Date: kc5tja 2018-11-26 18:16:20
Context
2019-03-13
07:11
Beginning specification work for the KCP53000B processor design. check-in: 04d68e52a6 user: kc5tja tags: trunk
2018-11-26
18:16
SIA IS PROVEN! The core worked fine. The problem was a bug in my ROMA core instantiation. Celebration time!! check-in: 3989d347ab user: kc5tja tags: trunk
07:36
Prove in hardware that the SIA core works. IT DOES. However, there is a bug when sending bytes with relatively few bits set on the low end of the byte (e.g., 0x05 becomes 0x0A on the receiver, while 0x51 remains 0x51 on the receiver). I genuinely have no idea how or why this is happening at this time. check-in: f70ab01418 user: kc5tja tags: trunk
Changes
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Changes to cores/step-2-dmac-roma-sia-test/roma-sia-test.v.

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	} = leds;

	assign leds = {
		issue_rom_read,
		read_rom_byte,
		issue_sia_write,
		wait_sia_ack,
		clk_50MHz,
		roma_a_valid,
		roma_a_ready,
		roma_d_valid
	};

	// The ROMA cannot be driven any faster than 50MHz.  Therefore,
	// we drive the whole system at 50MHz just to keep things simple.

	input wire i_clk_100MHz;
	reg clk_50MHz;

	always @(posedge i_clk_100MHz) begin
		clk_50MHz <= ~clk_50MHz;
	end

	// Here's our make-shift DMA controller.
	//
	// The RP register (Read Pointer) is a 24-bit address counter.
	// It's used to read through the flash ROM byte by byte.
	
	wire increment_read_pointer;
	wire issue_rom_read;

	reg [23:0] read_pointer;

	always @(posedge clk_50MHz) begin
		if(i_reset) begin
			read_pointer <= 24'h000000;	// Start at 1MB mark
		end
		else if(increment_read_pointer) begin
			read_pointer <= read_pointer + 1;
		end
	end

	// Here's where we drive the ROMA's private A-channel with the
................................................................................
	wire [2:0] roma_a_opcode;
        assign roma_a_opcode = `A_OPC_GET;
	wire [20:0] roma_a_address; // actually a word address!
	assign roma_a_address = {read_pointer[23:3], 3'b000};
	reg roma_a_valid;
	wire roma_a_ready;

	always @(posedge clk_50MHz) begin
		roma_a_valid <= 0;

		if(issue_rom_read) begin
			roma_a_valid <= 1;
		end
	end

................................................................................
	// Here's where we capture the data returned by the ROMA core.

	wire [63:0] roma_d_data;
	wire roma_d_valid;
	reg roma_d_ready;
	reg [7:0] fetched_byte;

	always @(posedge clk_50MHz) begin
		fetched_byte <= fetched_byte;
		roma_d_ready <= 0;

		if(read_rom_byte) begin
			roma_d_ready <= 1;
			if(roma_d_valid) begin
				case(read_pointer[2:0])
				3'd0: fetched_byte <= roma_d_data[7:0];
				3'd1: fetched_byte <= roma_d_data[15:8];
				3'd2: fetched_byte <= roma_d_data[23:16];
				3'd3: fetched_byte <= roma_d_data[31:23];
				3'd4: fetched_byte <= roma_d_data[39:32];
				3'd5: fetched_byte <= roma_d_data[47:40];
				3'd6: fetched_byte <= roma_d_data[55:48];
				3'd7: fetched_byte <= roma_d_data[63:56];
//				3'd0: fetched_byte <= 8'h11;
//				3'd1: fetched_byte <= 8'h22;
//				3'd2: fetched_byte <= 8'h33;
................................................................................
	// As I write this, this means no loopback, and 9600bps 8N1.

	reg sia_a_valid;
	wire sia_a_ready;
	wire sia_d_valid;
	wire sia_d_ready = wait_sia_ack;

	always @(posedge clk_50MHz) begin
		sia_a_valid <= 0;

		if(issue_sia_write) begin
			sia_a_valid <= 1;
		end
	end


	// Here's our state machine to drive the DMAC loop.
	
	reg [2:0] state;

	always @(posedge clk_50MHz) begin
		state <= state;

		if(i_reset) begin
			state <= 0;
		end
		else begin
			if(goto_1) begin
................................................................................

	output wire o_spi_mosi;
	input wire i_spi_miso;
	output wire o_spi_cs_n;
	output wire o_spi_clk;

	roma ROMA(
		.i_clk(clk_50MHz),
		.i_reset(i_reset),

		.i_a_opcode(roma_a_opcode),
		.i_a_address(roma_a_address),
		.i_a_source(2'd0),
		.i_a_valid(roma_a_valid),
		.o_a_ready(roma_a_ready),
................................................................................
		.o_spi_mosi(o_spi_mosi),
		.i_spi_miso(i_spi_miso),
		.o_spi_clk(flash_clk),
		.o_spi_cs(flash_cs)
	);

	oclkddr spi_ddr_clk(
		.i_clk(clk_50MHz),
		.i_ddr({1'b1, o_spi_cs_n}),
		.o_pin(o_spi_clk)
	);

	assign o_spi_cs_n = ~flash_cs;

	// The SIA core interfaces to the host PC.
................................................................................
	input wire i_rxd2;
	output wire o_rts2;

	assign o_txd2 = o_txd;
	assign o_rts2 = 0;

	sia #(
		.DEFAULT_DIVISOR(20'd5208)
	)
	SIA(
		.i_clk(clk_50MHz),
		.i_reset(i_reset),

		.i_a_opcode(`A_OPC_PUT_FULL),
		.i_a_source(2'd0),
		.i_a_size(`A_SIZ_BYTE),
		.i_a_mask(8'h01),
		.i_a_data({56'd0, fetched_byte}),







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	} = leds;

	assign leds = {
		issue_rom_read,
		read_rom_byte,
		issue_sia_write,
		wait_sia_ack,
		clk,
		roma_a_valid,
		roma_a_ready,
		roma_d_valid
	};

	// The ROMA cannot be driven any faster than 50MHz.  Therefore,
	// we drive the whole system at 50MHz just to keep things simple.

	input wire i_clk_100MHz;
	reg clk;

	always @(posedge i_clk_100MHz) begin
		clk <= ~clk;
	end

	// Here's our make-shift DMA controller.
	//
	// The RP register (Read Pointer) is a 24-bit address counter.
	// It's used to read through the flash ROM byte by byte.
	
	wire increment_read_pointer;
	wire issue_rom_read;

	reg [23:0] read_pointer;

	always @(posedge clk) begin
		if(i_reset) begin
			read_pointer <= 24'h000000;
		end
		else if(increment_read_pointer) begin
			read_pointer <= read_pointer + 1;
		end
	end

	// Here's where we drive the ROMA's private A-channel with the
................................................................................
	wire [2:0] roma_a_opcode;
        assign roma_a_opcode = `A_OPC_GET;
	wire [20:0] roma_a_address; // actually a word address!
	assign roma_a_address = {read_pointer[23:3], 3'b000};
	reg roma_a_valid;
	wire roma_a_ready;

	always @(posedge clk) begin
		roma_a_valid <= 0;

		if(issue_rom_read) begin
			roma_a_valid <= 1;
		end
	end

................................................................................
	// Here's where we capture the data returned by the ROMA core.

	wire [63:0] roma_d_data;
	wire roma_d_valid;
	reg roma_d_ready;
	reg [7:0] fetched_byte;

	always @(posedge clk) begin
		fetched_byte <= fetched_byte;
		roma_d_ready <= 0;

		if(read_rom_byte) begin
			roma_d_ready <= 1;
			if(roma_d_valid) begin
				case(read_pointer[2:0])
				3'd0: fetched_byte <= roma_d_data[7:0];
				3'd1: fetched_byte <= roma_d_data[15:8];
				3'd2: fetched_byte <= roma_d_data[23:16];
				3'd3: fetched_byte <= roma_d_data[31:24];
				3'd4: fetched_byte <= roma_d_data[39:32];
				3'd5: fetched_byte <= roma_d_data[47:40];
				3'd6: fetched_byte <= roma_d_data[55:48];
				3'd7: fetched_byte <= roma_d_data[63:56];
//				3'd0: fetched_byte <= 8'h11;
//				3'd1: fetched_byte <= 8'h22;
//				3'd2: fetched_byte <= 8'h33;
................................................................................
	// As I write this, this means no loopback, and 9600bps 8N1.

	reg sia_a_valid;
	wire sia_a_ready;
	wire sia_d_valid;
	wire sia_d_ready = wait_sia_ack;

	always @(posedge clk) begin
		sia_a_valid <= 0;

		if(issue_sia_write) begin
			sia_a_valid <= 1;
		end
	end


	// Here's our state machine to drive the DMAC loop.
	
	reg [2:0] state;

	always @(posedge clk) begin
		state <= state;

		if(i_reset) begin
			state <= 0;
		end
		else begin
			if(goto_1) begin
................................................................................

	output wire o_spi_mosi;
	input wire i_spi_miso;
	output wire o_spi_cs_n;
	output wire o_spi_clk;

	roma ROMA(
		.i_clk(clk),
		.i_reset(i_reset),

		.i_a_opcode(roma_a_opcode),
		.i_a_address(roma_a_address),
		.i_a_source(2'd0),
		.i_a_valid(roma_a_valid),
		.o_a_ready(roma_a_ready),
................................................................................
		.o_spi_mosi(o_spi_mosi),
		.i_spi_miso(i_spi_miso),
		.o_spi_clk(flash_clk),
		.o_spi_cs(flash_cs)
	);

	oclkddr spi_ddr_clk(
		.i_clk(clk),
		.i_ddr({1'b1, o_spi_cs_n}),
		.o_pin(o_spi_clk)
	);

	assign o_spi_cs_n = ~flash_cs;

	// The SIA core interfaces to the host PC.
................................................................................
	input wire i_rxd2;
	output wire o_rts2;

	assign o_txd2 = o_txd;
	assign o_rts2 = 0;

	sia #(
		.DEFAULT_DIVISOR(20'd5208) // 50MHz divisor for 9600bps
	)
	SIA(
		.i_clk(clk),
		.i_reset(i_reset),

		.i_a_opcode(`A_OPC_PUT_FULL),
		.i_a_source(2'd0),
		.i_a_size(`A_SIZ_BYTE),
		.i_a_mask(8'h01),
		.i_a_data({56'd0, fetched_byte}),