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Overview
Comment:Parameterize the SIA core.
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SHA3-256:315211fe32b71066db20535a69b39b2476030a95eefeac5f56caf1caaf8b5227
User & Date: kc5tja 2018-11-26 07:35:13
Context
2018-11-26
07:36
Prove in hardware that the SIA core works. IT DOES. However, there is a bug when sending bytes with relatively few bits set on the low end of the byte (e.g., 0x05 becomes 0x0A on the receiver, while 0x51 remains 0x51 on the receiver). I genuinely have no idea how or why this is happening at this time. check-in: f70ab01418 user: kc5tja tags: trunk
07:35
Parameterize the SIA core. check-in: 315211fe32 user: kc5tja tags: trunk
05:53
Fucking reset circuitry gets me every time! check-in: 8d2bf519df user: kc5tja tags: trunk
Changes
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Changes to cores/sia/rtl/verilog/sia.v.

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	o_irq,

	i_rxd,
	o_txd
);
	parameter		DIVISOR_BITS = 20;
	parameter		DEFAULT_DIVISOR = 10415;
	parameter		DIVHB = DIVISOR_BITS - 1;

	input			i_clk;
	input			i_reset;

	input	[2:0]		i_a_opcode;
	input	[1:0]		i_a_source;
................................................................................
	case(txd_loopback)
	2'b00:	o_txd = T_txd;
	2'b01:  o_txd = i_rxd;
	2'b10:  o_txd = 1'b0;
	2'b11:  o_txd = 1'b1;
	endcase

	sia_tilelink io(



		.i_clk(i_clk),
		.i_reset(i_reset),

		.o_txd_data(txd_data),
		.o_txd_valid(txd_valid),
		.i_txd_ready(txd_ready),
		.o_txd_loopback(txd_loopback),







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	o_irq,

	i_rxd,
	o_txd
);
	parameter		DIVISOR_BITS = 20;
	parameter		DEFAULT_DIVISOR = 20'd10415;
	parameter		DIVHB = DIVISOR_BITS - 1;

	input			i_clk;
	input			i_reset;

	input	[2:0]		i_a_opcode;
	input	[1:0]		i_a_source;
................................................................................
	case(txd_loopback)
	2'b00:	o_txd = T_txd;
	2'b01:  o_txd = i_rxd;
	2'b10:  o_txd = 1'b0;
	2'b11:  o_txd = 1'b1;
	endcase

	sia_tilelink #(
		.DEFAULT_DIVISOR(DEFAULT_DIVISOR)
	)
	io(
		.i_clk(i_clk),
		.i_reset(i_reset),

		.o_txd_data(txd_data),
		.o_txd_valid(txd_valid),
		.i_txd_ready(txd_ready),
		.o_txd_loopback(txd_loopback),

Changes to cores/sia/rtl/verilog/sia_tilelink/sia_tilelink.v.

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	o_d_param,
	o_d_error,
	o_d_valid,
	i_d_ready,

	o_irq
);


	input i_clk;
	input i_reset;

	input [2:0] i_a_opcode;
	input [1:0] i_a_source;
	input [1:0] i_a_size;
	// verilator lint_off UNUSED
................................................................................

	always @(posedge i_clk) begin
		r_baud <= r_baud;
		r_txd_loopback <= r_txd_loopback;
		r_rxd_loopback <= r_rxd_loopback;

		if(i_reset) begin
			r_baud <= 20'd10415;

			r_txd_loopback <= 0;
			r_rxd_loopback <= 0;
		end
		else if(wr_baud) begin
			if(i_a_mask[7]) begin
				r_txd_loopback <= i_a_data[63:62];
				r_rxd_loopback <= i_a_data[61];







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	o_d_param,
	o_d_error,
	o_d_valid,
	i_d_ready,

	o_irq
);
	parameter DEFAULT_DIVISOR = 20'd10415;	// 9600bps when clocked at 100MHz

	input i_clk;
	input i_reset;

	input [2:0] i_a_opcode;
	input [1:0] i_a_source;
	input [1:0] i_a_size;
	// verilator lint_off UNUSED
................................................................................

	always @(posedge i_clk) begin
		r_baud <= r_baud;
		r_txd_loopback <= r_txd_loopback;
		r_rxd_loopback <= r_rxd_loopback;

		if(i_reset) begin
//			r_baud <= 20'd10415;
			r_baud <= DEFAULT_DIVISOR;
			r_txd_loopback <= 0;
			r_rxd_loopback <= 0;
		end
		else if(wr_baud) begin
			if(i_a_mask[7]) begin
				r_txd_loopback <= i_a_data[63:62];
				r_rxd_loopback <= i_a_data[61];