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Overview
Comment:Integration test: SIA local loopback test passes!
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SHA3-256:2867a12bc11b204b0d20609bcdc64a4073ddf210f70538d3e8d285920342adc1
User & Date: kc5tja 2018-11-25 02:03:32
Context
2018-11-25
02:29
Forgot to remove debugging change to default loopback settings check-in: 5511953cec user: kc5tja tags: trunk
02:03
Integration test: SIA local loopback test passes! check-in: 2867a12bc1 user: kc5tja tags: trunk
02:03
Bug fix: Draw the loopback control bits from the proper data lines. check-in: 8fe7daff6e user: kc5tja tags: trunk
Changes
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Changes to cores/sia/bench/cpp/sia.cpp.

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	}

	~TESTBENCH() {
		delete m_core;
		m_core = NULL;
	}

	virtual	void	opentrace(const char *vcdname) {
		if (!m_trace) {
			m_trace = new VerilatedVcdC;
			m_core->trace(m_trace, 99);
			m_trace->open(vcdname);
		}
	}

	virtual	void	closetrace(void) {
		if (m_trace) {
			m_trace->close();
			delete m_trace;
			m_trace = NULL;
		}
	}

	virtual void reset() {
printf("Reset tick()\n");
		m_core->i_reset = 1;

		this->tick();
		m_core->i_reset = 0;
printf("Reset complete()\n");
	}

	virtual void tick() {
		m_ticks++;

		m_core->i_clk = 0;
		m_core->eval();
		if (m_trace) {
printf("Pre edge trace\n");
			m_trace->dump((vluint64_t)(10*m_ticks-2));
		}

		m_core->i_clk = 1;
		m_core->eval();
		if (m_trace) {
printf("Rising edge trace\n");
			m_trace->dump((vluint64_t)(10*m_ticks));
		}

		m_core->i_clk = 0;
		m_core->eval();
		if (m_trace) {
printf("Falling edge trace\n");
			m_trace->dump((vluint64_t)(10*m_ticks+5));
			m_trace->flush();
fflush(stdout);
		}
	}

	virtual	void	eval(void) {












		m_core->eval();
	}


	virtual bool is_done() {
		return Verilated::gotFinish();





	}

































































};


int
main(int argc, char **argv, char **env) {
	Verilated::commandArgs(argc, argv);
	TESTBENCH<Vsia> *tb = new TESTBENCH<Vsia>();
................................................................................
	// This enables interrupts for RXD data valid and overrun conditions,
	// and puts the receiver into local loopback with the transmitter.
	// That way, we can write to SIA.TXOUT and just busy-wait on o_irq
	// until it's asserted.  When it's asserted, we can verify that RXINP
	// contains the byte we just transmitted, and that we didn't overrun
	// in the process.
	
	io->i_a_opcode = A_OPC_PUT_FULL;
	io->i_a_size = A_SIZ_BYTE;

	io->i_a_mask = 0x08;
	io->i_a_data = 0x03 << 24;
	io->i_a_source = 2;
	io->i_a_valid = 1;



	io->i_d_ready = 1;






	tb->tick();





	assert(io->o_d_valid);
	assert(io->o_d_source == 2);
	assert(io->o_d_opcode == D_OPC_ACK);

	exit(0);
}








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	}

	~TESTBENCH() {
		delete m_core;
		m_core = NULL;
	}

	virtual	void opentrace(const char *vcdname) {
		if (!m_trace) {
			m_trace = new VerilatedVcdC;
			m_core->trace(m_trace, 99);
			m_trace->open(vcdname);
		}
	}

	virtual	void closetrace(void) {
		if (m_trace) {
			m_trace->close();
			delete m_trace;
			m_trace = NULL;
		}
	}

	virtual void reset() {

		m_core->i_reset = 1;
		m_core->i_rxd = 1;
		this->tick();
		m_core->i_reset = 0;

	}

	virtual void tick() {
		m_ticks++;

		m_core->i_clk = 0;
		m_core->eval();
		if (m_trace) {

			m_trace->dump((vluint64_t)(10*m_ticks-2));
		}

		m_core->i_clk = 1;
		m_core->eval();
		if (m_trace) {

			m_trace->dump((vluint64_t)(10*m_ticks));
		}

		m_core->i_clk = 0;
		m_core->eval();
		if (m_trace) {

			m_trace->dump((vluint64_t)(10*m_ticks+5));
			m_trace->flush();

		}
	}

	virtual bool is_done() {
		return Verilated::gotFinish();
	}

	virtual void write_byte(int address, uint8_t byte) {
		int mask = 1 << (address & 7);
		uint64_t bus = (byte << (8 * (address & 7)));

		m_core->i_a_opcode = A_OPC_PUT_FULL;
		m_core->i_a_size = A_SIZ_BYTE;
		m_core->i_a_mask = mask;
		m_core->i_a_data = bus;
		m_core->i_a_source = 2;
		m_core->i_a_valid = 1;

		m_core->i_d_ready = 1;



		int timeout = 100;
		do {
			this->tick();
			timeout--;
		} while(!m_core->o_d_valid && (timeout > 0));
		
		assert(timeout > 0);
		assert(m_core->o_d_valid);
		assert(m_core->o_d_source == 2);
		assert(m_core->o_d_opcode == D_OPC_ACK);

		m_core->i_d_ready = 0;
		m_core->i_a_valid = 0;
	}

	virtual void write_word(int address, uint32_t word) {
		assert((address & 3) == 0);

		int upper_word = (address & 4);
		uint64_t bus = ((uint64_t)(word) << (8 * upper_word));

		m_core->i_a_opcode = A_OPC_PUT_FULL;
		m_core->i_a_size = A_SIZ_WORD;
		m_core->i_a_mask = 0xF << upper_word;
		m_core->i_a_data = bus;
		m_core->i_a_source = 2;
		m_core->i_a_valid = 1;

		m_core->i_d_ready = 1;

		int timeout = 100;
		do {
			this->tick();
			timeout--;
		} while(!m_core->o_d_valid && (timeout > 0));
		
		assert(timeout > 0);
		assert(m_core->o_d_valid);
		assert(m_core->o_d_source == 2);
		assert(m_core->o_d_opcode == D_OPC_ACK);

		m_core->i_d_ready = 0;
		m_core->i_a_valid = 0;
	}

	virtual uint32_t read_word(int address) {
		int upper_word = address & 4;

		assert((address & 3) == 0);

		m_core->i_a_opcode = A_OPC_GET;
		m_core->i_a_size = A_SIZ_WORD;
		m_core->i_a_mask = (0x0F << upper_word);
		m_core->i_a_data = 0;
		m_core->i_a_source = 2;
		m_core->i_a_valid = 1;

		m_core->i_d_ready = 1;

		int timeout = 100;
		do {
			tick();
			timeout--;
		} while(!m_core->o_d_valid && (timeout > 0));

		assert(timeout > 0);
		assert(m_core->o_d_valid);
		assert(m_core->o_d_source == 2);
		assert(m_core->o_d_opcode == D_OPC_ACK_DATA);
		return (uint32_t)(m_core->o_d_data >> (8 * upper_word));
	}
};


int
main(int argc, char **argv, char **env) {
	Verilated::commandArgs(argc, argv);
	TESTBENCH<Vsia> *tb = new TESTBENCH<Vsia>();
................................................................................
	// This enables interrupts for RXD data valid and overrun conditions,
	// and puts the receiver into local loopback with the transmitter.
	// That way, we can write to SIA.TXOUT and just busy-wait on o_irq
	// until it's asserted.  When it's asserted, we can verify that RXINP
	// contains the byte we just transmitted, and that we didn't overrun
	// in the process.
	
	tb->write_byte(0x03, 0x03);


	uint32_t baud_value = tb->read_word(0x04);
	tb->write_word(0x04, baud_value | 0x20000000);



	// At this point, we should be able to start writing bytes to the SIA.
	// After each byte is written, we wait for an interrupt.  That will
	// indicate the successful receipt of a byte over local loopback.

	tb->write_byte(0x00, 0xAA);

	{
		int timeout = 153600; // Yeah, this can take a while.
		do {
			tb->tick();
			timeout--;
		} while(!io->o_irq && (timeout > 0));
		assert(timeout > 0);
		assert(io->o_irq);
	}




	exit(0);
}