About the Kestrel-2DX

The Kestrel-2DX is a home computer whose design, both hardware and core system software, is licensed under a free/libre license. Except where otherwise noted, all content in this repository, both hardware and software, are licensed under the Mozilla Public License, V2.0.

The Kestrel-2DX is primarily influenced by the Jupiter Cantab Jupiter Ace computer. This computer represents what is possible when taking a minimal approach to design. In many ways, the Kestrel-2DX represents a similar, minimalistic approach to home computer design. Although the processor responds to interrupts, for instance, no standard peripherals use them. The processor is fast enough to keep up without needing asynchronous interruptions to service peripherals.

The Kestrel-2DX consists of several cooperating components, discussed below.

Kestrel-2DX Block Diagram

Central Processing Unit (KCP53000)

The base Kestrel-2DX configuration runs on a single KCP53000 processor. This core implements a 64-bit, RISC-V, M-mode only instruction set. Although it is clocked at 25MHz, on average it requires four clocks per instruction1, thus delivering roughly 6MIPS performance.

The CPU is illustrated as a single core in the above diagram; however, it actually is broken down into several components itself:

Core Purpose
PolarisCPU The actual processing engine.
arbiter This core takes the separate instruction and data buses of the CPU and merges them into a single bus, suitable for a Von Neumann architecture computer.
bottleneck This core is responsible for reducing the 64-bit data path to a 16-bit data path suitable for use on the FPGA development board.
bridge This core is responsible for exposing the processor's native bus as a Wishbone B.3 compatible interface.

The details of each of these components can be found in their respective Verilog source files, and is otherwise beyond the scope of this document.

General Purpose I/O Adapter

The GPIA core is responsible for interfacing the Kestrel to the outside world. It offers 16 bits of dedicated inputs, and 16 bits of dedicated outputs. The Kestrel-2DX uses the GPIA primarily for these purposes:

  • Address the SD card,
  • Provides visibility into the HSYNC and VSYNC signals for gaming purposes,
  • Select which block of RAM the MGIA fetches video data from, and,
  • Addressing the diagnostic LEDs on the Digilent Nexys-2 FPGA board.

Access to the SD card occurs at a data rate of roughly 4KiB per second (32 Kbps).

The diagnostic LEDs are rarely used in practice, and are intended only for systems-level bring-up in the event system firmware crashes prior to getting the MGIA drivers initialized. They are also unofficially used to indicate SD card transfer activity. These signals may be re-used for other purposes in the future.

Keyboard Interface Adapter

The KIA core connects a PS/2-compatible keyboard to the computer.2 This core maintains a 16-byte queue of raw PS/2 scancodes on behalf of the Kestrel-2DX. This allows the Kestrel-2DX to function without needing interrupts, greatly simplifying the overall system design.


The Kestrel-2DX has a very small amount of memory; just enough to bring up the rest of the computer. In includes two types:

  • Random Access Memory, RAM, which is where programs are loaded into from storage, and,
  • Read-Only Memory, ROM, which is used to hold the basic I/O primitives useful for programs running in RAM.


When fabricated on a Spartan XC3S1200E FPGA, 48KiB of internal block memory is available spread across three 16KiB blocks, as shown in the block diagram. This memory is used to hold the contents of the current screen, any operating system that is currently resident, along with the user's application programs.


The system firmware contains a copy of the BIOS, or Basic Input/Output System. The BIOS lets applications poll the keyboard, send textual output to the display without having to worry about its bitmapped nature, and load and save information from the internal SD card.

Monochrome Graphics Interface Adapter

The Kestrel-2DX includes a custom display core, the MGIA, which is responsible for displaying a 640x200, monochrome, bitmapped image to the screen.

Unlike most video interfaces, the function of the MGIA is entirely hard-wired. The core offers no user-accessible registers, and is heavily dependent on the way the FPGA's block memory works to allow video refresh without interfering with the CPU's performance.

If you're interested in reusing the display logic in your own project, the MGIA offers a 16-bit Wishbone B.3 master interface3, which can be used with almost any other Wishbone-compatible memory source.

Expansion Address Space

In addition to the resources discussed above, the Kestrel-2DX allots 16MB of address space for future expansions. These expansions come from modifications to the core Verilog source listings comprising the Kestrel-2DX project. As of this writing, no expansions are defined.

Programming Environment

While the Kestrel-2DX was intended to have a built-in programming language resident in ROM, it turned out that synthesizing the ROM takes up too much chip real-estate to meet minimum performance requirements. For this reason, the desired programming environment must be loaded from SD card.

This may change in a future revision of the Kestrel-2DX design. However, in the event that a future revision allows a ROM-resident language, the ability to load a replacement environment from SD card will be provided.

1: The shortest KCP53000 instruction requires only two clock cycles, while the longest requires eight. However, a typical mix of instructions will involve arithmetic or logic instructions, each requiring 3 clocks, memory reads/writes (5 to 7 clocks), and branches (4 clocks). Heuristically, this averages out to 4 clocks best-case, and 4.6 clocks worst-case.

2: However, with appropriate software, it can also be used with a mouse as well. Unfortunately, the KIA cannot be used to interface a keyboard and a mouse at the same time.

3: The MGIA core actually exposes a proper subset of the Wishbone B.3 required signals. The signals which are not explicitly exposed can be trivially synthesized. The subset exposed was chosen to work well with Xilinx Spartan-3 block RAMs.