.PHONY: test_sia_tilelink
test_sia_tilelink:
	(cd rtl/verilog/sia_tilelink && sby -f sia_tilelink.sby)

.PHONY: test_transmit_engine
test_transmit_engine:
	(cd rtl/verilog/transmit_engine && sby -f transmit_engine.sby)

.PHONY: test_receiver_engine
test_receiver_engine:
	(cd rtl/verilog/receiver_engine && sby -f receiver_engine.sby)

obj_dir: rtl/verilog/sia_tilelink/*.v rtl/verilog/receiver_engine/*.v rtl/verilog/transmit_engine/*.v rtl/verilog/sia.v bench/cpp/*.cpp
	verilator -Wall --trace -y rtl/verilog/sia_tilelink	\
	-y rtl/verilog/receiver_engine			\
	-y rtl/verilog/transmit_engine			\
	-y rtl/verilog					\
	-y ../include/verilog				\
	-CFLAGS "-I../../include/cpp"			\
	-cc sia.v					\
	--top-module sia				\
	--exe bench/cpp/sia.cpp

driver: obj_dir
	make -j -C obj_dir -f Vsia.mk Vsia

.PHONY:
verilator_test: driver
	obj_dir/Vsia

.PHONY: test
test: test_sia_tilelink test_transmit_engine test_receiver_engine verilator_test
