Kestrel 2DX

Nexys-2 Expansion Port

Nexys-2 Expansion Port

The Nexys-2 FPGA board has no on-board static RAM. Its only source of RAM is either the on-chip block RAM, or the pseudo-SDRAM chip. To gain access to legitimate static RAM, I must use my icoBoard Gamma as a RAM expansion card. This requires running 36 wires from the Nexys-2 to the icoBoard Gamma.

I will use three PMOD ports bonded together to make a single "expansion port." This page documents the current "standard" for this interconnect. I don't expect to have to advance the standard too far; if/when the Kestrel 3 becomes available, I expect a very different expansion architecture to become more prominent.

Pin Descriptions

The "pin-out" below is preliminary.

Pins Signal Driver ALE Purpose
1-16 A1-A16 Master 1 Address bits A1-A16.
D0-D15 either 0 Data bits D0-D15.
17-18 A17-A18 Master 1 Address bits A17-A18.
WS1-WS0 Master 0 Write Strobes.
19 A19 Master 1 Address bit A19.
ACK Slave 0 Asserted by the slave to indicate data on D0-D15 is valid.
20-23 A20-A23 Master 1 Address bits A20-A23.
1 Master 0 Unassigned.
24 ALE Master --- Address Latch Enable.

The ALE signal can double as a clock, of sorts; when high, all I/Os are driven by the master and presents the top-most 23 bits of a 24-bit address. This allows the expansion port to address 16MB of memory. When ALE is low, however, the I/Os may change directions and be driven by the slave (e.g., as with a read operation).

The ALE frequency cannot exceed 25MHz; however, in practice, it will likely run much slower than this. (E.g., 12.5MHz or 6.25MHz.)

The following table describes how one can tell a read from a write transaction:

WS1 WS0 Operation
0 0 Read data on D0-D15
0 1 Write data D0-D7 only
1 0 Write data D8-D15 only
1 1 Write data D0-D15

Unassigned Signals

All unassigned signals must be driven by the master with a logic 1. Unassigned signals must be ignored by the attached slave.

Revisions of this standard can be made in a way that preserves legacy hardware compatibility. Any of the unassigned signals can become inputs at a later time with the help of a pull-up resistor on the master side of the circuit.

New hardware can be made compatible with legacy expansion ports by using series resistors. If the slave expects to be able to drive a currently undefined signal, it must do so through a resistor so as to not dead-short a legacy expansion port pin.