# Development Roadmap

## Basic Bringup

10.  Get FPGA board to come up with predictable LED arrangement.
15.  Make clock divider from 50MHz down to 100kHz.
20.  Synthesize CPU with hardwired data bus set to $0013.  Attach address pins A15-A8 to LEDs.  Should see activity on LEDs.  Remember that LEDs are active-LOW.
30.  Replace hardwired $0013 with a synthesized ROM.
40.  Introduce GPIA and address decoder modules; wire LEDs to the GPIA output port.  Rewrite firmware to do blinky-lights via the GPIA.
50.  Introduce IPL RAM.  Firmware to copy itself into RAM; otherwise identical to previous step.
60.  Introduce MGIA and video RAM.  Rewrite firmware to display sign-on banner.  Replace old clock divider with MGIA's derived clock.
70.  Introduce KIA.  Rewrite firmware to add full-screen notepad app, a la Atari 400/800 without a cartridge.

## Mass Storage Bringup

TBD.  This is a much, *much* bigger problem due to how complex the SD protocol is, even over SPI.  Plus, I need to work on a persistent storage layout/filesystem layout.  I *might* be able to re-use the original Kestrel-2's layout, but remember that it's built only for a 16-bit CPU.  I might have to rewrite the tools used to create initial filesystem images, though; the older tools are written in an ugly combination of Forth, Go, and I'm sure one other language.  They should all be rewritten into a consistent language for ease of maintenance.

It's occurred to me that I should be recording these in tickets, not in the wiki.