Memory Map

The original Kestrel 2 computer had a memory map as follows:

After replacing the CPU, we need to redesign the memory layout. My current thinking on layout is:

Addresses not explicitly listed above either aren't assigned or are mirrors of previous address decode domains.

IPL Resources

The ROM has sufficient space to hold around 28KiB worth of executable code, considering 4KiB for font and keyboard tables. Thus, the ROM image can hold about 7000 CPU instructions. This ought to be sufficient for just about any exploratory applications I can think of by a large margin; it actually ought to be large enough for a simple mono-tasking kernel and a BASIC-like interactive programming environment.

The IPL RAM is internal block RAM, always available for use by the ROM image. It also doubles as the source of video data for the MGIA core. All together, the IPL RAM can provide up to three 16KB pages of video, which you can select with some bits set in the GPIA output register. If required, the last 384 bytes of video RAM may also be used for data storage without affecting the displayed image. At cold-boot, $10000-$13E80 is selected as the default video page.

Expansion Memory

The 16MB of expansion memory exists to explore interfacing with external memory. For the Nexys-2, this means designing a simple bus interface that bridges to my iCE40 FPGA board, which happens to have a 1MB SRAM chip on it. For the DE-1 board, it comes pre-equipped with 512KB of SRAM, so that resource would appear here.

I/O Space

The I/O space contains memory-mapped I/O resources familiar to Kestrel 2 programmers: the GPIA, KIA, etc. Additional cores may appear (e.g., SIA) if required.