Firenet

Check-in [18ac40a7b9]
Login

Check-in [18ac40a7b9]

Many hyperlinks are disabled.
Use anonymous login to enable hyperlinks.

Overview
Comment:Use PNG not GIF for images
Timelines: family | ancestors | descendants | both | NEWNET
Files: files | file ages | folders
SHA1: 18ac40a7b9f847a0b9e4bf05eee5d8fe258d5292
User & Date: jim 2014-12-20 11:00:52.282
Context
2016-01-03
11:01
QueFinder added & odetojoy show check-in: 9778542a31 user: jim tags: NEWNET
2014-12-20
11:00
Use PNG not GIF for images check-in: 18ac40a7b9 user: jim tags: NEWNET
2014-06-26
19:14
Did copper pour on board check-in: 10beb15f1a user: jim tags: NEWNET
Changes
Unified Diff Ignore Whitespace Patch
Changes to Docs/firenet.lyx.
︙︙
13681
13682
13683
13684
13685
13686
13687
13688
13689
13690
13691
13692
13693
13694
13695

sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename Images/node_outside.gif
	display false
	scale 15

\end_inset


\end_layout








|








13681
13682
13683
13684
13685
13686
13687
13688
13689
13690
13691
13692
13693
13694
13695

sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename Images/node_outside.png
	display false
	scale 15

\end_inset


\end_layout
︙︙
13737
13738
13739
13740
13741
13742
13743
13744
13745
13746
13747
13748
13749
13750
13751

sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename Images/node_inside.gif
	display false
	scale 15

\end_inset


\end_layout








|








13737
13738
13739
13740
13741
13742
13743
13744
13745
13746
13747
13748
13749
13750
13751

sideways false
status open

\begin_layout Plain Layout
\noindent
\align center
\begin_inset Graphics
	filename Images/node_inside.png
	display false
	scale 15

\end_inset


\end_layout
︙︙
Changes to Docs/firenet.pdf.

cannot compute difference between binary files

Changes to Hardware/Board/pcbnotes.txt. 
1
2
3
4

5
6
7
8
9
10
11

PCB Notes:

	Bring up board
	Pick CAM JOB

	Once Up pick File->Open Job		Use sfe-gerb274X.cam in L-Apps/Eagle/cam
	
	Note specify file destination for each layer
	Then run process. (i.e. another directory...
	as it picks / and you cannot write there)
	
	Also open the execllon job file L-Apps/Eagle/cam and




|
>








1
2
3
4
5
6
7
8
9
10
11
12

PCB Notes:

	Bring up board
	Pick CAM JOB	- Button on board window
		then
	Once Up pick File->Open Job		Use sfe-gerb274X.cam in L-Apps/Eagle/cam
	
	Note specify file destination for each layer
	Then run process. (i.e. another directory...
	as it picks / and you cannot write there)
	
	Also open the execllon job file L-Apps/Eagle/cam and
︙︙
34
35
36
37
38
39
40



41
42
43












	
Discard:
	FlowI2C.dri		- Drill info
	FlowI2C.gpi		- Gerber plot info
		
	Archive all to a zip and send for design rule check
	



	
	Viewer found on VM: Fedora 11 Use Gerbv
						Problem with GBO



















>
>
>



>
>
>
>
>
>
>
>
>
>
>

35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58

	
Discard:
	FlowI2C.dri		- Drill info
	FlowI2C.gpi		- Gerber plot info
		
	Archive all to a zip and send for design rule check
	
	Have size of board for input on form Go to Advanced Circuits 
	then to PCB link on page.
	
	
	Viewer found on VM: Fedora 11 Use Gerbv
						Problem with GBO
						
						
Solder stop Component side (.STC)	= 20 Dimension layer + 29 tStop layer
 Silkscreen Component side (.PLC)	= 20 Dimension layer + 21 tPlace layer + 25 tNames layer
             Componentside (.CMP)	= 1 Top layer + 17 Pads layer + 18 Vias layer + 20 Dimension layer

               Solderside (.SOL)	= 16 Bot layer + 17 Pads layer + 18 Vias layer + 20 Dimension layer
  Solder stop Solder side (.STS)	= 30 bStop layer + 20 Dimension layer
   Silkscreen Solder side (.PLS)	= 22 bPlace layer + 26 bNames layer + 20 Dimension layer

           Excellon drill (.DRD)	= 44 Drills layer + 45 Holes laye