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<title>MOVSLDUP: Move Packed Single-FP Low and Duplicate (x86 Instruction Set Reference)</title>
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<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>MOVSLDUP: Move Packed Single-FP Low and Duplicate (x86 Instruction Set Reference)</title>
<h1>MOVSLDUP</h1>
<h2>Move Packed Single-FP Low and Duplicate</h2>
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<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
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<td class="grid"><code>F3 0F 12 /r</code></td>
<td class="grid"><code>MOVSLDUP xmm1, xmm2/m128</code></td>
<td class="grid">Move 128 bits representing packed SP data elements from xmm2/m128 to xmm1 register and duplicate low.</td>
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<th>Description</th>
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<td class="instruction_set_reference_box">
<p>The linear address corresponds to the address of the least-significant byte of the referenced memory data. When a memory address is indicated, the 16 bytes of data at memory location m128 are loaded and the single-precision elements in positions 0 and 2 are duplicated. When the register-register form of this operation is used, the same operation is performed but with data coming from the 128-bit source register.</p>
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<td class="instruction_set_reference_box">
<pre><span class="keyword">if</span><span class="operator">(</span>source <span class="operator">==</span> m128<span class="operator">)</span> {
	<span class="comment">//load instruction</span>
	xmm1<span class="operator">[</span><span class="number">0..31</span><span class="operator">]</span> <span class="operator">=</span> m128<span class="operator">[</span><span class="number">0..31</span><span class="operator">]</span><span class="operator">;</span>
	xmm1<span class="operator">[</span><span class="number">32..63</span><span class="operator">]</span> <span class="operator">=</span> m128<span class="operator">[</span><span class="number">0..31</span><span class="operator">]</span>
	xmm1<span class="operator">[</span><span class="number">64..95</span><span class="operator">]</span> <span class="operator">=</span> m128<span class="operator">[</span><span class="number">64..95</span><span class="operator">]</span><span class="operator">;</span>
	xmm1<span class="operator">[</span><span class="number">96..127</span><span class="operator">]</span> <span class="operator">=</span> m128<span class="operator">[</span><span class="number">64..95</span><span class="operator">]</span><span class="operator">;</span>
}
<span class="keyword">else</span> {
	<span class="comment">//move instruction</span>
	xmm1<span class="operator">[</span><span class="number">0..31</span><span class="operator">]</span> <span class="operator">=</span> xmm2<span class="operator">[</span><span class="number">0..31</span><span class="operator">]</span><span class="operator">;</span>
	xmm1<span class="operator">[</span><span class="number">32..63</span><span class="operator">]</span> <span class="operator">=</span> xmm2<span class="operator">[</span><span class="number">0..31</span><span class="operator">]</span><span class="operator">;</span>
	xmm1<span class="operator">[</span><span class="number">64..95</span><span class="operator">]</span> <span class="operator">=</span> xmm2<span class="operator">[</span><span class="number">64..95</span><span class="operator">]</span><span class="operator">;</span>
	xmm1<span class="operator">[</span><span class="number">96..127</span><span class="operator">]</span> <span class="operator">=</span> xmm2<span class="operator">[</span><span class="number">64..95</span><span class="operator">]</span><span class="operator">;</span>
}
</pre>
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<th>Exceptions</th>
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<td class="instruction_set_reference_box">
General protection exception if not aligned on 16-byte boundary, regardless of segment.
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<th>Numeric Exceptions</th>
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None.
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<th>Protected Mode Exceptions</th>
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<tr><td><code>#GP(0)</code></td><td>For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.</td></tr>
<tr><td><code>#GP(0)</code></td><td>For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.</td></tr>
<tr><td><code>#SS(0)</code></td><td>For an illegal address in the SS segment.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>For a page fault.</td></tr>
<tr><td><code>#NM</code></td><td>If TS bit in CR0 is set.</td></tr>
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<th>Real-Address Mode Exceptions</th>
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<tr><td><code>#GP(0)</code></td><td>If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH.</td></tr>
<tr><td><code>#NM</code></td><td>If TS bit in CR0 is set.</td></tr>
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<th>Virtual-8086 Mode Exceptions</th>
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<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH.</td></tr>
<tr><td><code>#NM</code></td><td>If TS bit in CR0 is set.</td></tr>
<tr><td><code>#UD</code></td><td>If CR0.EM = 1. If CR4.OSFXSR(bit 9) = 0. If CPUID.SSE3(ECX bit 0) = 0.</td></tr>
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<object>
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<th>Instruction</th>
<th>Latency</th>
<th>Throughput</th>
<th>Execution Unit</th>
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<tr><td class="grid"><code>CPUID</code></td><td class="grid">0F3n</td><td class="grid">0F3n</td><td class="grid">0F3n</td></tr>
<tr><td class="grid"><code>MOVSLDUP xmm1, xmm2</code></td><td class="grid">6</td><td class="grid">2</td><td class="grid">FP_MOVE</td></tr>
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