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<title>MOVLPD: Move Low Packed Double-Precision Floating-Point Value (x86 Instruction Set Reference)</title>
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<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>MOVLPD: Move Low Packed Double-Precision Floating-Point Value (x86 Instruction Set Reference)</title>
<h1>MOVLPD</h1>
<h2>Move Low Packed Double-Precision Floating-Point Value</h2>
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<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
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<td class="grid"><code>66 0F 12 /r</code></td>
<td class="grid"><code>MOVLPD xmm, m64</code></td>
<td class="grid">Move double-precision floating-point value from m64 to low quadword of xmm register.</td>
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<td class="grid"><code>66 0F 13 /r</code></td>
<td class="grid"><code>MOVLPD m64, xmm</code></td>
<td class="grid">Move double-precision floating-point nvalue from low quadword of xmm register to m64.</td>
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<th>Description</th>
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<p>Moves a double-precision floating-point value from the source operand (second operand) to the destination operand (first operand). The source and destination operands can be an XMM register or a 64-bit memory location. This instruction allows a double-precision floating-point value to be moved to and from the low quadword of an XMM register and memory. It cannot be used for register to register or memory to memory moves. When the destination operand is an XMM register, the high quadword of the register remains unchanged.</p>
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<pre><span class="comment">//MOVLPD instruction for memory to XMM move:</span>
<span class="keyword">if</span><span class="operator">(</span>IsXMM<span class="operator">(</span>Destination<span class="operator">)</span><span class="operator">)</span> Destination<span class="operator">[</span><span class="number">0..63</span><span class="operator">]</span> <span class="operator">=</span> Source<span class="operator">;</span>
<span class="comment">//Destination[64..127] unchanged</span>
<span class="comment">//MOVLPD instruction for XMM to memory move:</span>
<span class="keyword">else</span> Destination <span class="operator">=</span> Source<span class="operator">[</span><span class="number">0..63</span><span class="operator">]</span><span class="operator">;</span>
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<th>SIMD Floating-Point Exceptions</th>
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None.
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<th>Protected Mode Exceptions</th>
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<tr><td><code>#GP(0)</code></td><td>For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.</td></tr>
<tr><td><code>#GP(0)</code></td><td>For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.</td></tr>
<tr><td><code>#SS(0)</code></td><td>For an illegal address in the SS segment.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>For a page fault.</td></tr>
<tr><td><code>#NM</code></td><td>If TS in CR0 is set.</td></tr>
<tr><td><code>#UD</code></td><td>If EM in CR0 is set. If OSFXSR in CR4 is 0. If CPUID feature flag SSE2 is 0.</td></tr>
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<th>Real-Address Mode Exceptions</th>
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<tr><td><code>#GP(0)</code></td><td>If any part of the operand lies outside the effective address space from 0 to FFFFH.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If any part of the operand lies outside the effective address space from 0 to FFFFH.</td></tr>
<tr><td><code>#NM</code></td><td>If TS in CR0 is set.</td></tr>
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<th>Virtual-8086 Mode Exceptions</th>
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Same exceptions as in Real Address Mode
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<tr><td><code>#PF(fault-code)</code></td><td>For a page fault.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>For a page fault.</td></tr>
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