Fresh IDE . Check-in [59c17aeab1]
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Overview
Comment:Added new instruction set reference. Not full, but is pretty helpful because contains the flags affected and explain the instructions in details.
Timelines: family | ancestors | descendants | both | trunk
Files: files | file ages | folders
SHA1:59c17aeab1922a8d50bc2fec59835d96a0736a35
User & Date: johnfound 2017-09-22 16:00:35
Context
2017-10-24
13:38
The FlatAssembler compiler has been updated to the official milestone version 1.72; check-in: d01cfe6750 user: johnfound tags: trunk
08:28
Updated the help system to allow raw headless html files and to decorate them in the same way as the .md files.

The extension of such files is .rhtm; The FASM LaTeX manual has been updated to the latest version and formatted to .rhtm file. The doc/tools/ directory was cleaned up from outdated tools and LaTeX_to_html tool (tth) has been updated to the latest version. Notice, that in doc/tools/tth_src is a modified version of the tool that emits anchor tags in a way, Fresh IDE help system use them.

This help files update is part of preparations for the new release of Fresh IDE together with "newskin" branch. check-in: c8ad2b898b user: johnfound tags: help_update

2017-10-07
14:04
Work on changing all icons to PNG with transparency, rendered from vector icons. Support for several sizes of the icons and light and dark Desktop themes. check-in: e7b54ee4c4 user: johnfound tags: newskin
2017-09-22
16:00
Added new instruction set reference. Not full, but is pretty helpful because contains the flags affected and explain the instructions in details. check-in: 59c17aeab1 user: johnfound tags: trunk
2017-09-09
13:57
Different implementation of show/hide component palette not using IsWindowVisible. check-in: c59d12fb90 user: johnfound tags: trunk
Changes
Hide Diffs Unified Diffs Ignore Whitespace Patch

Changes to doc/index.help.

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; For details, read the chapter "Fresh IDE - tips and tricks"
;
; The format of this file is:  TITLE | FILENAME
; All files are searched from %FreshHelp% path.
; The lines starting with ";" is comment. The empty lines are ignored.
;

Help index				|	index.md
FASM manual				|	FASM.html

FreshLib reference			|	FreshLibRef.md
FreshLib user guide			|	FreshLibUserGuide.md

FreshLib object oriented programming	|	FreshLibOOP.md
Fresh IDE - advanced setup		|	advanced_setup.md
Fresh IDE - tips and tricks		|	tips.md
Linux system calls reference		|	lscr/index.idx







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; For details, read the chapter "Fresh IDE - tips and tricks"
;
; The format of this file is:  TITLE | FILENAME
; All files are searched from %FreshHelp% path.
; The lines starting with ";" is comment. The empty lines are ignored.
;

Help index                              |       index.md
x86 instruction set                     |       x86/x86.idx
FASM manual                             |       FASM.html
FreshLib reference                      |       FreshLibRef.md

FreshLib user guide                     |       FreshLibUserGuide.md
FreshLib object oriented programming    |       FreshLibOOP.md
Fresh IDE - advanced setup              |       advanced_setup.md
Fresh IDE - tips and tricks             |       tips.md
Linux system calls reference            |       lscr/index.idx

Added doc/x86/html/file_module_x86_id_1.html.





















































































































































































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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>AAA: ASCII Adjust After Addition (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>AAA: ASCII Adjust After Addition (x86 Instruction Set Reference)</title>
<h1>AAA</h1>
<h2>ASCII Adjust After Addition</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>37</code></td>
<td class="grid"><code>AAA</code></td>
<td class="grid">ASCII adjust AL after addition</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Adjusts the sum of two unpacked BCD values to create an unpacked BCD result. The AL register is the implied source and destination operand for this instruction. The AAA instruction is only useful when it follows an ADD instruction that adds (binary addition) two unpacked BCD values and stores a byte result in the AL register. The AAA instruction then adjusts the contents of the AL register to contain the correct 1-digit unpacked BCD result.</p>
<p>If the addition produces a decimal carry, the AH register increments by 1, and the CF and AF flags are set. If there was no decimal carry, the CF and AF flags are cleared and the AH register is unchanged. In either case, bits 4 through 7 of the AL register are set to 0.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre><span class="keyword">if</span><span class="operator">(</span><span class="operator">(</span>AL <span class="operator">&amp;</span> <span class="number">0xF</span><span class="operator">)</span> <span class="operator">&gt;</span> <span class="number">9</span> <span class="operator">||</span> AF <span class="operator">==</span> <span class="number">1</span><span class="operator">)</span> {
	AL <span class="operator">=</span> AL <span class="operator">+</span> <span class="number">6</span><span class="operator">;</span>
	AH <span class="operator">=</span> AH <span class="operator">+</span> <span class="number">1</span><span class="operator">;</span>
	AF <span class="operator">=</span> <span class="number">1</span><span class="operator">;</span>
	CF <span class="operator">=</span> <span class="number">1</span>
}
<span class="keyword">else</span> {
	AF <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
	CF <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
}
AL <span class="operator">=</span> AL <span class="operator">&amp;</span> <span class="number">0xF</span><span class="operator">;</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>The AF and CF flags are set to 1 if the adjustment results in a decimal carry; otherwise they are set to 0. The OF, SF, ZF, and PF flags are undefined.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
None.
</td>
</tr>
</table>
</object>
</div>
</body>
</html>

Added doc/x86/html/file_module_x86_id_10.html.















































































































































































































































































































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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>ADDSUBPD: Packed Double-FP Add/Subtract (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>ADDSUBPD: Packed Double-FP Add/Subtract (x86 Instruction Set Reference)</title>
<h1>ADDSUBPD</h1>
<h2>Packed Double-FP Add/Subtract</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>66 0F D0 /r</code></td>
<td class="grid"><code>ADDSUBPD xmm1, xmm2/m128</code></td>
<td class="grid">Add/Subtract packed DP FP numbers from xmm2/m128 to xmm1.</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Adds the double-precision floating-point values in the high quadword of the source and destination operands and stores the result in the high quadword of the destination operand.</p>
<p>Subtracts the double-precision floating-point value in the low quadword of the source operand from the low quadword of the destination operand and stores the result in the low quadword of the destination operand.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre>xmm1<span class="operator">[</span><span class="number">0..63</span><span class="operator">]</span> <span class="operator">=</span> xmm1<span class="operator">[</span><span class="number">0..63</span><span class="operator">]</span> <span class="operator">-</span> xmm2/m128<span class="operator">[</span><span class="number">0..63</span><span class="operator">]</span><span class="operator">;</span>
xmm1<span class="operator">[</span><span class="number">64..127</span><span class="operator">]</span> <span class="operator">=</span> xmm1<span class="operator">[</span><span class="number">64..127</span><span class="operator">]</span> <span class="operator">+</span> xmm2/m128<span class="operator">[</span><span class="number">64..127</span><span class="operator">]</span><span class="operator">;</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
When the source operand is a memory operand, it must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated.
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Numeric Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
Overflow, Underflow, Invalid, Precision, Denormal.
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#GP(0)</code></td><td>For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#SS(0)</code></td><td>For an illegal address in the SS segment.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>For a page fault.</td></tr>
<tr><td><code>#NM</code></td><td>If TS bit in CR0 is set.</td></tr>
<tr><td><code>#XM</code></td><td>For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT = 1).</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#NM</code></td><td>If TS bit in CR0 is set.</td></tr>
<tr><td><code>#XM</code></td><td>For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT = 1).</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#NM</code></td><td>If TS bit in CR0 is set. 3-34 #XM For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT = 1).</td></tr>
<tr><td><code>#UD</code></td><td>If CR0.EM = 1. For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT = 0). If CR4.OSFXSR(bit 9) = 0. If CPUID.SSE3(ECX bit 0) = 0.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Instruction</th>
<th>Latency</th>
<th>Throughput</th>
<th>Execution Unit</th>
</tr>
<tr><td class="grid"><code>CPUID</code></td><td class="grid">0F3n</td><td class="grid">0F3n</td><td class="grid">0F3n</td></tr>
<tr><td class="grid"><code>ADDSUBPD</code></td><td class="grid">5</td><td class="grid">2</td><td class="grid">FP_ADD</td></tr>
</table>
</object>
</div>
</body>
</html>

Added doc/x86/html/file_module_x86_id_100.html.









































































































































































































































































































































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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>FLD: Load Floating Point Value (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>FLD: Load Floating Point Value (x86 Instruction Set Reference)</title>
<h1>FLD</h1>
<h2>Load Floating Point Value</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>D9 /0</code></td>
<td class="grid"><code>FLD m32fp</code></td>
<td class="grid">Push m32fp onto the FPU register stack.</td>
</tr>
<tr>
<td class="grid"><code>DD /0</code></td>
<td class="grid"><code>FLD m64fp</code></td>
<td class="grid">Push m64fp onto the FPU register stack.</td>
</tr>
<tr>
<td class="grid"><code>DB /5</code></td>
<td class="grid"><code>FLD m80fp</code></td>
<td class="grid">Push m80fp onto the FPU register stack.</td>
</tr>
<tr>
<td class="grid"><code>D9 C0+i</code></td>
<td class="grid"><code>FLD ST(i)</code></td>
<td class="grid">Push ST(i) onto the FPU register stack.</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Pushes the source operand onto the FPU register stack. The source operand can be in singleprecision, double-precision, or double extended-precision floating-point format. If the source operand is in single-precision or double-precision floating-point format, it is automatically converted to the double extended-precision floating-point format before being pushed on the stack.</p>
<p>The FLD instruction can also push the value in a selected FPU register [ST(i)] onto the stack.</p>
<p>Here, pushing register ST(0) duplicates the stack top.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre><span class="keyword">if</span><span class="operator">(</span>Source <span class="operator">==</span> ST<span class="operator">(</span>i<span class="operator">)</span><span class="operator">)</span> Temporary <span class="operator">=</span> ST<span class="operator">(</span>i<span class="operator">)</span><span class="operator">;</span>
Top <span class="operator">=</span> Top <span class="operator">-</span> <span class="number">1</span><span class="operator">;</span>
<span class="keyword">if</span><span class="operator">(</span>IsMemoryOperand<span class="operator">(</span>Source<span class="operator">)</span><span class="operator">)</span> ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span> <span class="operator">=</span> ConvertToExtendedDouble<span class="operator">(</span>Source<span class="operator">)</span><span class="operator">;</span>
<span class="keyword">else</span> ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span> <span class="operator">=</span> Temporary<span class="operator">;</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>FPU flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>C1 Set to 1 if stack overflow occurred; otherwise, set to 0.
C0, C2, C3 Undefined.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Floating-Point Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#IS</code></td><td>Stack overflow occurred.</td></tr>
<tr><td><code>#IS</code></td><td>Stack overflow occurred.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#D</code></td><td>Source operand is a denormal value. Does not occur if the source operand is in double extended-precision floating-point format.</td></tr>
<tr><td><code>#D</code></td><td>Source operand is a denormal value. Does not occur if the source operand is in double extended-precision floating-point format.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#GP</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#SS</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
</div>
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLDLN2/FLDZ: Load Constant (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLDLN2/FLDZ: Load Constant (x86 Instruction Set Reference)</title>
<h1>FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLDLN2/FLDZ</h1>
<h2>Load Constant</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>D9 E8</code></td>
<td class="grid"><code>FLD1</code></td>
<td class="grid">Push +1.0 onto the FPU register stack.</td>
</tr>
<tr>
<td class="grid"><code>D9 E9</code></td>
<td class="grid"><code>FLDL2T</code></td>
<td class="grid">Push log_2(10) onto the FPU register stack.</td>
</tr>
<tr>
<td class="grid"><code>D9 EA</code></td>
<td class="grid"><code>FLDL2E</code></td>
<td class="grid">Push log_2(e) onto the FPU register stack.</td>
</tr>
<tr>
<td class="grid"><code>D9 EB</code></td>
<td class="grid"><code>FLDPI</code></td>
<td class="grid">Push pi onto the FPU register stack.</td>
</tr>
<tr>
<td class="grid"><code>D9 EC</code></td>
<td class="grid"><code>FLDLG2</code></td>
<td class="grid">Push log_10(2) onto the FPU register stack.</td>
</tr>
<tr>
<td class="grid"><code>D9 ED</code></td>
<td class="grid"><code>FLDLN2</code></td>
<td class="grid">Push log_e(2) onto the FPU register stack.</td>
</tr>
<tr>
<td class="grid"><code>D9 EE</code></td>
<td class="grid"><code>FLDZ</code></td>
<td class="grid">Push +0.0 onto the FPU register stack.</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Push one of seven commonly used constants (in double extended-precision floating-point format) onto the FPU register stack. The constants that can be loaded with these instructions include +1.0, +0.0, log_10(2), log_e(2), pi, log_2(10), and log_2(e). For each constant, an internal 66-bit constant is rounded (as specified by the RC field in the FPU control word) to double extendedprecision floating-point format. The inexact-result exception (#P) is not generated as a result of the rounding, nor is the C1 flag set in the x87 FPU status word if the value is rounded up.</p>
<p>See the section titled &quot;Pi&quot; in Chapter 8 of the IA-32 Intel Architecture Software Developer's Manual, Volume 1, for a description of the pi constant.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre>Top <span class="operator">=</span> Top <span class="operator">-</span> <span class="number">1</span><span class="operator">;</span>
ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span> <span class="operator">=</span> Constant<span class="operator">;</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>FPU flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>C1 Set to 1 if stack overflow occurred; otherwise, set to 0.
C0, C2, C3 Undefined.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>IA-32 Architecture Compatibility</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>When the RC field is set to round-to-nearest, the FPU produces the same constants that is produced by the Intel 8087 and Intel 287 math coprocessors.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Floating-Point Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#IS</code></td><td>Stack overflow occurred.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
</div>
</body>
</html>

Added doc/x86/html/file_module_x86_id_102.html.





















































































































































































































































































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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>FLDCW: Load x87 FPU Control Word (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>FLDCW: Load x87 FPU Control Word (x86 Instruction Set Reference)</title>
<h1>FLDCW</h1>
<h2>Load x87 FPU Control Word</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>D9 /5</code></td>
<td class="grid"><code>FLDCW m2byte</code></td>
<td class="grid">Load FPU control word from m2byte.</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Loads the 16-bit source operand into the FPU control word. The source operand is a memory location. This instruction is typically used to establish or change the FPU's mode of operation.</p>
<p>If one or more exception flags are set in the FPU status word prior to loading a new FPU control word and the new control word unmasks one or more of those exceptions, a floating-point exception will be generated upon execution of the next floating-point instruction (except for the no-wait floating-point instructions, see the section titled &quot;Software Exception Handling&quot; in Chapter 8 of the IA-32 Intel Architecture Software Developer's Manual, Volume 1). To avoid raising exceptions when changing FPU operating modes, clear any pending exceptions (using the FCLEX or FNCLEX instruction) before loading the new control word.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre>FPUControlWord <span class="operator">=</span> Source<span class="operator">;</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>FPU flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>C0, C1, C2, C3 undefined.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Floating-Point Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
None; however, this operation might unmask a pending exception in the FPU status word. That exception is then generated upon execution of the next &quot;waiting&quot; floating-point instruction.
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#GP</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#SS</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
</div>
</body>
</html>

Added doc/x86/html/file_module_x86_id_103.html.







































































































































































































































































































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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>FLDENV: Load x87 FPU Environment (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>FLDENV: Load x87 FPU Environment (x86 Instruction Set Reference)</title>
<h1>FLDENV</h1>
<h2>Load x87 FPU Environment</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>D9 /4</code></td>
<td class="grid"><code>FLDENV m14/28byte</code></td>
<td class="grid">Load FPU environment from m14byte or m28byte.</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Loads the complete x87 FPU operating environment from memory into the FPU registers. The source operand specifies the first byte of the operating-environment data in memory. This data is typically written to the specified memory location by a FSTENV or FNSTENV instruction.</p>
<p>The FPU operating environment consists of the FPU control word, status word, tag word, instruction pointer, data pointer, and last opcode. Figures 8-9 through 8-12 in the IA-32 Intel Architecture Software Developer's Manual, Volume 1, show the layout in memory of the loaded environment, depending on the operating mode of the processor (protected or real) and the current operand-size attribute (16-bit or 32-bit). In virtual-8086 mode, the real mode layouts are used.</p>
<p>The FLDENV instruction should be executed in the same operating mode as the corresponding FSTENV/FNSTENV instruction.</p>
<p>If one or more unmasked exception flags are set in the new FPU status word, a floating-point exception will be generated upon execution of the next floating-point instruction (except for the no-wait floating-point instructions, see the section titled &quot;Software Exception Handling&quot; in Chapter 8 of the IA-32 Intel Architecture Software Developer's Manual, Volume 1). To avoid generating exceptions when loading a new environment, clear all the exception flags in the FPU status word that is being loaded.</p>
<p>If a page or limit fault occurs during the execution of this instruction, the state of the x87 FPU registers as seen by the fault handler may be different than the state being loaded from memory.</p>
<p>In such situations, the fault handler should ignore the status of the x87 FPU registers, handle the fault, and return. The FLDENV instruction will then complete the loading of the x87 FPU registers with no resulting context inconsistency.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre>FPUControlWord <span class="operator">=</span> Source<span class="operator">.</span>FPUControlWord<span class="operator">;</span>
FPUStatusWord <span class="operator">=</span> Source<span class="operator">.</span>FPUStatusWord<span class="operator">;</span>
FPUTagWord <span class="operator">=</span> Source<span class="operator">.</span>FPUTagWord<span class="operator">;</span>
FPUDataPointer <span class="operator">=</span> Source<span class="operator">.</span>FPUDataPointer<span class="operator">;</span>
FPUInstructionPointer <span class="operator">=</span> Source<span class="operator">.</span>FPUInstructionPointer<span class="operator">;</span>
FPULastInstructionOpcode <span class="operator">=</span> Source<span class="operator">.</span>FPULastInstructionOpcode<span class="operator">;</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>FPU flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>The C0, C1, C2, C3 flags are loaded.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Floating-Point Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
None; however, if an unmasked exception is loaded in the status word, it is generated upon execution of the next &quot;waiting&quot; floating-point instruction.
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#GP</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#SS</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
</div>
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>FMUL/FMULP/FIMUL: Multiply (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>FMUL/FMULP/FIMUL: Multiply (x86 Instruction Set Reference)</title>
<h1>FMUL/FMULP/FIMUL</h1>
<h2>Multiply</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>D8 /1</code></td>
<td class="grid"><code>FMUL m32fp</code></td>
<td class="grid">Multiply ST(0) by m32fp and store result in ST(0)</td>
</tr>
<tr>
<td class="grid"><code>DC /1</code></td>
<td class="grid"><code>FMUL m64fp</code></td>
<td class="grid">Multiply ST(0) by m64fp and store result in ST(0)</td>
</tr>
<tr>
<td class="grid"><code>D8 C8+i</code></td>
<td class="grid"><code>FMUL ST(0), ST(i)</code></td>
<td class="grid">Multiply ST(0) by ST(i) and store result in ST(0)</td>
</tr>
<tr>
<td class="grid"><code>DC C8+i</code></td>
<td class="grid"><code>FMUL ST(i), ST(0)</code></td>
<td class="grid">Multiply ST(i) by ST(0) and store result in ST(i)</td>
</tr>
<tr>
<td class="grid"><code>DE C8+i</code></td>
<td class="grid"><code>FMULP ST(i), ST(0)</code></td>
<td class="grid">Multiply ST(i) by ST(0), store result in ST(i), and pop the register stack</td>
</tr>
<tr>
<td class="grid"><code>DE C9</code></td>
<td class="grid"><code>FMULP</code></td>
<td class="grid">Multiply ST(1) by ST(0), store result in ST(1), and pop the register stack</td>
</tr>
<tr>
<td class="grid"><code>DA /1</code></td>
<td class="grid"><code>FIMUL m32int</code></td>
<td class="grid">Multiply ST(0) by m32int and store result in ST(0)</td>
</tr>
<tr>
<td class="grid"><code>DE /1</code></td>
<td class="grid"><code>FIMUL m16int</code></td>
<td class="grid">Multiply ST(0) by m16int and store result in ST(0)</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Multiplies the destination and source operands and stores the product in the destination location.</p>
<p>The destination operand is always an FPU data register; the source operand can be an FPU data register or a memory location. Source operands in memory can be in single-precision or doubleprecision floating-point format or in word or doubleword integer format.</p>
<p>The no-operand version of the instruction multiplies the contents of the ST(1) register by the contents of the ST(0) register and stores the product in the ST(1) register. The one-operand version multiplies the contents of the ST(0) register by the contents of a memory location (either a floating point or an integer value) and stores the product in the ST(0) register. The two-operand version, multiplies the contents of the ST(0) register by the contents of the ST(i) register, or vice versa, with the result being stored in the register specified with the first operand (the destination operand).</p>
<p>The FMULP instructions perform the additional operation of popping the FPU register stack after storing the product. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1. The no-operand version of the floating-point multiply instructions always results in the register stack being popped. In some assemblers, the mnemonic for this instruction is FMUL rather than FMULP.</p>
<p>The FIMUL instructions convert an integer source operand to double extended-precision floating-point format before performing the multiplication.</p>
<p>The sign of the result is always the exclusive-OR of the source signs, even if one or more of the values being multiplied is 0 or infinite. When the source operand is an integer 0, it is treated as a +0.</p>
<p>The following table shows the results obtained when multiplying various classes of numbers, assuming that neither overflow nor underflow occurs.</p>
<div>
<table class="grid">
<caption>FMUL/FMULP/FIMUL Results</caption>
<tr><td>-</td><td>Destination: -inf</td><td>Destination: -F</td><td>Destination: -0</td><td>Destination: +0</td><td>Destination: +F</td><td>Destination: +inf</td><td>Destination: NaN</td></tr>
<tr><td>Source: -inf</td><td>+inf</td><td>+inf</td><td>*</td><td>*</td><td>-inf</td><td>-inf</td><td>NaN</td></tr>
<tr><td>Source: -F</td><td>+inf</td><td>+F</td><td>+0</td><td>-0</td><td>-F</td><td>-inf</td><td>NaN</td></tr>
<tr><td>Source: -I</td><td>+inf</td><td>+F</td><td>+0</td><td>-0</td><td>-F</td><td>-inf</td><td>NaN</td></tr>
<tr><td>Source: -0</td><td>*</td><td>+0</td><td>+0</td><td>-0</td><td>-0</td><td>*</td><td>NaN</td></tr>
<tr><td>Source: +0</td><td>*</td><td>-0</td><td>-0</td><td>+0</td><td>+0</td><td>*</td><td>NaN</td></tr>
<tr><td>Source: +I</td><td>-inf</td><td>-F</td><td>-0</td><td>+0</td><td>+F</td><td>+inf</td><td>NaN</td></tr>
<tr><td>Source: +F</td><td>-inf</td><td>-F</td><td>-0</td><td>+0</td><td>+F</td><td>+inf</td><td>NaN</td></tr>
<tr><td>Source: +inf</td><td>-inf</td><td>-inf</td><td>*</td><td>*</td><td>+inf</td><td>+inf</td><td>NaN</td></tr>
<tr><td>Source: NaN</td><td>NaN</td><td>NaN</td><td>NaN</td><td>NaN</td><td>NaN</td><td>NaN</td><td>NaN</td></tr>
<tfoot>
<tr><td colspan="8">F Means finite floating-point value.</td></tr>
<tr><td colspan="8">I Means Integer.</td></tr>
<tr><td colspan="8">* Indicates invalid-arithmetic-operand (#IA) exception.</td></tr>
</tfoot>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre><span class="keyword">if</span><span class="operator">(</span>Instruction <span class="operator">==</span> FIMUL<span class="operator">)</span> Destination <span class="operator">=</span> Destination <span class="operator">*</span> ConvertToExtendedDouble<span class="operator">(</span>Source<span class="operator">)</span><span class="operator">;</span>
<span class="keyword">else</span> Destination <span class="operator">=</span> Destination <span class="operator">*</span> Source<span class="operator">;</span> <span class="comment">//source operand is floating-point value</span>

<span class="keyword">if</span><span class="operator">(</span>Instruction <span class="operator">==</span> FMULP<span class="operator">)</span> PopRegisterStack<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>FPU flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>C1 Set to 0 if stack underflow occurred.
Set if result was rounded up; cleared otherwise.
C0, C2, C3 Undefined.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Floating-Point Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#IS</code></td><td>Stack underflow occurred.</td></tr>
<tr><td><code>#IS</code></td><td>Stack underflow occurred.</td></tr>
<tr><td><code>#IA</code></td><td>Operand is an SNaN value or unsupported format. One operand is +-0 and the other is +-infinite.</td></tr>
<tr><td><code>#D</code></td><td>Source operand is a denormal value.</td></tr>
<tr><td><code>#U</code></td><td>Result is too small for destination format.</td></tr>
<tr><td><code>#O</code></td><td>Result is too large for destination format.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#GP</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#SS</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Instruction</th>
<th>Latency</th>
<th>Throughput</th>
<th>Execution Unit</th>
</tr>
<tr><td class="grid"><code>CPUID</code></td><td class="grid">0F3n/0F2n</td><td class="grid">0F3n/0F2n</td><td class="grid">0F2n</td></tr>
<tr><td class="grid"><code>FMUL</code></td><td class="grid">8/7</td><td class="grid">2/2</td><td class="grid">FP_MUL</td></tr>
</table>
</object>
</div>
</body>
</html>

Added doc/x86/html/file_module_x86_id_105.html.











































































































































































































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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>FNOP: No operation (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>FNOP: No operation (x86 Instruction Set Reference)</title>
<h1>FNOP</h1>
<h2>No operation</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>D9 D0</code></td>
<td class="grid"><code>FNOP</code></td>
<td class="grid">No operation is performed.</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Performs no FPU operation. This instruction takes up space in the instruction stream but does not affect the FPU or machine context, except the EIP register.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Floating-Point Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
None.
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
</div>
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>FPATAN: Partial Arctangent (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>FPATAN: Partial Arctangent (x86 Instruction Set Reference)</title>
<h1>FPATAN</h1>
<h2>Partial Arctangent</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>D9 F3</code></td>
<td class="grid"><code>FPATAN</code></td>
<td class="grid">Replace ST(1) with arctan(ST(1)/ST(0)) and pop the register stack.</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Computes the arctangent of the source operand in register ST(1) divided by the source operand in register ST(0), stores the result in ST(1), and pops the FPU register stack. The result in register ST(0) has the same sign as the source operand ST(1) and a magnitude less than +infinite.</p>
<p>The FPATAN instruction returns the angle between the X axis and the line from the origin to the point (X,Y), where Y (the ordinate) is ST(1) and X (the abscissa) is ST(0). The angle depends on the sign of X and Y independently, not just on the sign of the ratio Y/X. This is because a point (-X,Y) is in the second quadrant, resulting in an angle between pi/2 and pi, while a point (X,-Y) is in the fourth quadrant, resulting in an angle between 0 and -pi/2. A point (- X,-Y) is in the third quadrant, giving an angle between -pi/2 and -pi.</p>
<p>The following table shows the results obtained when computing the arctangent of various classes of numbers, assuming that underflow does not occur.</p>
<div>
<table class="grid">
<caption>FPATAN Results</caption>
<tr><td>-</td><td>ST(0): -inf</td><td>ST(0): -F</td><td>ST(0): -0</td><td>ST(0): +0</td><td>ST(0): +F</td><td>ST(0): +inf</td><td>ST(0): NaN</td></tr>
<tr><td>ST(1): -inf</td><td>-3p/4*</td><td>-p/2</td><td>-p/2</td><td>-p/2</td><td>-p/2</td><td>-p/4*</td><td>NaN</td></tr>
<tr><td>ST(1): -F</td><td>-p</td><td>-p</td><td>to</td><td>-p/2</td><td>-p/2</td><td>-p/2</td><td>-p/2</td><td>to</td><td>-0</td><td>-0</td><td>NaN</td></tr>
<tr><td>ST(1): -0</td><td>-p</td><td>-p</td><td>-p*</td><td>-0*</td><td>-0</td><td>-0</td><td>NaN</td></tr>
<tr><td>ST(1): +0</td><td>+p</td><td>+p</td><td>+p*</td><td>+0*</td><td>+0</td><td>+0</td><td>NaN</td></tr>
<tr><td>ST(1): +F</td><td>+p</td><td>+p</td><td>to</td><td>+p/2</td><td>+p/2</td><td>+p/2</td><td>+p/2</td><td>to</td><td>+0</td><td>+0</td><td>NaN</td></tr>
<tr><td>ST(1): +inf</td><td>+3p/4*</td><td>+p/2</td><td>+p/2</td><td>+p/2</td><td>+p/2</td><td>+p/4*</td><td>NaN</td></tr>
<tr><td>ST(1): NaN</td><td>NaN</td><td>NaN</td><td>NaN</td><td>NaN</td><td>NaN</td><td>NaN</td><td>NaN</td></tr>
<tfoot>
<tr><td colspan="8">F Means finite floating-point value.</td></tr>
<tr><td colspan="8">* Table 8-10 in the IA-32 Intel Architecture Software Developer's Manual, Volume 1, specifies that the ratios 0/0 and infinite/infinite generate the floating-point invalid arithmetic-operation exception and, if this exception is masked, the floating-point QNaN indefinite value is returned. With the FPATAN instruction, the 0/0 or infinite/infinite value is actually not calculated using division. Instead, the arctangent of the two variables is derived from a standard mathematical formulation that is generalized to allow complex numbers as arguments. In this complex variable formulation, arctangent(0,0) etc. has well defined values. These values are needed to develop a library to compute transcendental functions with complex arguments, based on the FPU functions that only allow floating-point values as arguments.</td></tr>
</tfoot>
</table>
</div>
<p>There is no restriction on the range of source operands that FPATAN can accept.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre>ST<span class="operator">(</span><span class="number">1</span><span class="operator">)</span> <span class="operator">=</span> ArcTangent<span class="operator">(</span>ST<span class="operator">(</span><span class="number">1</span><span class="operator">)</span> / ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
PopRegisterStack<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>FPU flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>C1 Set to 0 if stack underflow occurred.
Set if result was rounded up; cleared otherwise.
C0, C2, C3 Undefined.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>IA-32 Architecture Compatibility</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>The source operands for this instruction are restricted for the 80287 math coprocessor to the following range:
0 &lt;= |ST(1)| &lt; |ST(0)| &lt; +infinite
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Floating-Point Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#IS</code></td><td>Stack underflow occurred.</td></tr>
<tr><td><code>#IS</code></td><td>Stack underflow occurred.</td></tr>
<tr><td><code>#IA</code></td><td>Source operand is an SNaN value or unsupported format.</td></tr>
<tr><td><code>#D</code></td><td>Source operand is a denormal value.</td></tr>
<tr><td><code>#U</code></td><td>Result is too small for destination format.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Instruction</th>
<th>Latency</th>
<th>Throughput</th>
<th>Execution Unit</th>
</tr>
<tr><td class="grid"><code>CPUID</code></td><td class="grid">0F3n/0F2n</td><td class="grid">0F3n/0F2n</td><td class="grid">0F2n</td></tr>
<tr><td class="grid"><code>FPATAN</code></td><td class="grid">220-300/150-300</td><td class="grid">140</td><td class="grid">-</td></tr>
</table>
</object>
</div>
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>FPREM: Partial Remainder (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>FPREM: Partial Remainder (x86 Instruction Set Reference)</title>
<h1>FPREM</h1>
<h2>Partial Remainder</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>D9 F8</code></td>
<td class="grid"><code>FPREM</code></td>
<td class="grid">Replace ST(0) with the remainder obtained from dividing ST(0) by ST(1).</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Computes the remainder obtained from dividing the value in the ST(0) register (the dividend) by the value in the ST(1) register (the divisor or modulus), and stores the result in ST(0). The remainder represents the following value: Remainder = ST(0) - (Q * ST(1)) Here, Q is an integer value that is obtained by truncating the floating-point number quotient of [ST(0) / ST(1)] toward zero. The sign of the remainder is the same as the sign of the dividend. The magnitude of the remainder is less than that of the modulus, unless a partial remainder was computed (as described below).</p>
<p>This instruction produces an exact result; the inexact-result exception does not occur and the rounding control has no effect. The following table shows the results obtained when computing the remainder of various classes of numbers, assuming that underflow does not occur.</p>
<div>
<table class="grid">
<caption>FPREM Results</caption>
<tr><td>-</td><td>ST(0): -inf</td><td>ST(0): -F</td><td>ST(0): -0</td><td>ST(0): +0</td><td>ST(0): +F</td><td>ST(0): +inf</td><td>ST(0): NaN</td></tr>
<tr><td>ST(1): -inf</td><td>*</td><td>*</td><td>*</td><td>*</td><td>*</td><td>*</td><td>NaN</td></tr>
<tr><td>ST(1): -F</td><td>ST(0)</td><td>-F</td><td>or</td><td>-0</td><td>**</td><td>**</td><td>-F</td><td>or</td><td>-0</td><td>ST(0)</td><td>NaN</td></tr>
<tr><td>ST(1): -0</td><td>-0</td><td>-0</td><td>*</td><td>*</td><td>-0</td><td>-0</td><td>NaN</td></tr>
<tr><td>ST(1): +0</td><td>+0</td><td>+0</td><td>*</td><td>*</td><td>+0</td><td>+0</td><td>NaN</td></tr>
<tr><td>ST(1): +F</td><td>ST(0)</td><td>+F</td><td>or</td><td>+0</td><td>**</td><td>**</td><td>+F</td><td>or</td><td>+0</td><td>ST(0)</td><td>NaN</td></tr>
<tr><td>ST(1): +inf</td><td>*</td><td>*</td><td>*</td><td>*</td><td>*</td><td>*</td><td>NaN</td></tr>
<tr><td>ST(1): NaN</td><td>NaN</td><td>NaN</td><td>NaN</td><td>NaN</td><td>NaN</td><td>NaN</td><td>NaN</td></tr>
<tfoot>
<tr><td colspan="8">F Means finite floating-point value.</td></tr>
<tr><td colspan="8">* Indicates floating-point invalid-arithmetic-operand (#IA) exception.</td></tr>
<tr><td colspan="8">** Indicates floating-point zero-divide (#Z) exception.</td></tr>
</tfoot>
</table>
</div>
<p>When the result is 0, its sign is the same as that of the dividend. When the modulus is infinite, the result is equal to the value in ST(0).</p>
<p>The FPREM instruction does not compute the remainder specified in IEEE Std 754. The IEEE specified remainder can be computed with the FPREM1 instruction. The FPREM instruction is provided for compatibility with the Intel 8087 and Intel287 math coprocessors.</p>
<p>The FPREM instruction gets its name &quot;partial remainder&quot; because of the way it computes the remainder. This instructions arrives at a remainder through iterative subtraction. It can, however, reduce the exponent of ST(0) by no more than 63 in one execution of the instruction.</p>
<p>If the instruction succeeds in producing a remainder that is less than the modulus, the operation is complete and the C2 flag in the FPU status word is cleared. Otherwise, C2 is set, and the result in ST(0) is called the partial remainder. The exponent of the partial remainder will be less than the exponent of the original dividend by at least 32. Software can re-execute the instruction (using the partial remainder in ST(0) as the dividend) until C2 is cleared. (Note that while executing such a remainder-computation loop, a higher-priority interrupting routine that needs the FPU can force a context switch in-between the instructions in the loop.) An important use of the FPREM instruction is to reduce the arguments of periodic functions.</p>
<p>When reduction is complete, the instruction stores the three least-significant bits of the quotient in the C3, C1, and C0 flags of the FPU status word. This information is important in argument reduction for the tangent function (using a modulus of pi/4), because it locates the original angle in the correct one of eight sectors of the unit circle.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre>D <span class="operator">=</span> GetExponent<span class="operator">(</span>ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span> <span class="operator">-</span> GetExponent<span class="operator">(</span>ST<span class="operator">(</span><span class="number">1</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
<span class="keyword">if</span><span class="operator">(</span>D <span class="operator">&lt;</span> <span class="number">64</span><span class="operator">)</span> {
	Q <span class="operator">=</span> Integer<span class="operator">(</span>TruncateTowardZero<span class="operator">(</span>ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span> / ST<span class="operator">(</span><span class="number">1</span><span class="operator">)</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
	ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span> <span class="operator">=</span> ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span> <span class="operator">-</span> <span class="operator">(</span>ST<span class="operator">(</span><span class="number">1</span><span class="operator">)</span> <span class="operator">*</span> Q<span class="operator">)</span><span class="operator">;</span>
	C0 <span class="operator">=</span> GetLeastSignificantBit<span class="operator">(</span>Q2<span class="operator">)</span><span class="operator">;</span>
	C1 <span class="operator">=</span> GetLeastSignificantBit<span class="operator">(</span>Q0<span class="operator">)</span><span class="operator">;</span>
	C2 <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
	C3 <span class="operator">=</span> GetLeastSignificantBit<span class="operator">(</span>Q1<span class="operator">)</span><span class="operator">;</span>
}
<span class="keyword">else</span> {
	C2 <span class="operator">=</span> <span class="number">1</span><span class="operator">;</span>
	N <span class="operator">=</span> Constant<span class="operator">;</span> <span class="comment">//This is an implementation-dependent number between 32 and 63.</span>
	QQ <span class="operator">=</span> Integer<span class="operator">(</span>TruncateTowardZero<span class="operator">(</span><span class="operator">(</span>ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span> / ST<span class="operator">(</span><span class="number">1</span><span class="operator">)</span><span class="operator">)</span> / <span class="number">2</span> <span class="operator">*</span> <span class="operator">(</span>D <span class="operator">-</span> N<span class="operator">)</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
	ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span> <span class="operator">=</span> ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span> <span class="operator">-</span> <span class="operator">(</span>ST<span class="operator">(</span><span class="number">1</span><span class="operator">)</span> <span class="operator">*</span> QQ <span class="operator">*</span> <span class="number">2</span><span class="operator">(</span>D <span class="operator">-</span> N<span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
}
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>FPU flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>C0 Set to bit 2 (Q2) of the quotient.
C1 Set to 0 if stack underflow occurred; otherwise, set to least significant bit
of quotient (Q0).
C2 Set to 0 if reduction complete; set to 1 if incomplete.
C3 Set to bit 1 (Q1) of the quotient.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Floating-Point Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#IS</code></td><td>Stack underflow occurred.</td></tr>
<tr><td><code>#IS</code></td><td>Stack underflow occurred.</td></tr>
<tr><td><code>#IA</code></td><td>Source operand is an SNaN value, modulus is 0, dividend is infinite, or unsupported</td></tr>
<tr><td><code>#D</code></td><td>Source operand is a denormal value.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
</div>
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>FPREM1: Partial Remainder (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>FPREM1: Partial Remainder (x86 Instruction Set Reference)</title>
<h1>FPREM1</h1>
<h2>Partial Remainder</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>D9 F5</code></td>
<td class="grid"><code>FPREM1</code></td>
<td class="grid">Replace ST(0) with the IEEE remainder obtained from dividing ST(0) by ST(1).</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Computes the IEEE remainder obtained from dividing the value in the ST(0) register (the dividend) by the value in the ST(1) register (the divisor or modulus), and stores the result in ST(0).</p>
<p>The remainder represents the following value: Remainder = ST(0) - (Q * ST(1)) Here, Q is an integer value that is obtained by rounding the floating-point number quotient of [ST(0) / ST(1)] toward the nearest integer value. The magnitude of the remainder is less than or equal to half the magnitude of the modulus, unless a partial remainder was computed (as described below).</p>
<p>This instruction produces an exact result; the precision (inexact) exception does not occur and the rounding control has no effect. The following table shows the results obtained when computing the remainder of various classes of numbers, assuming that underflow does not occur.</p>
<div>
<table class="grid">
<caption>FPREM1 Results</caption>
<tr><td>-</td><td>ST(0): -inf</td><td>ST(0): -F</td><td>ST(0): -0</td><td>ST(0): +0</td><td>ST(0): +F</td><td>ST(0): +inf</td><td>ST(0): NaN</td></tr>
<tr><td>ST(1): -inf</td><td>*</td><td>*</td><td>*</td><td>*</td><td>*</td><td>*</td><td>NaN</td></tr>
<tr><td>ST(1): -F</td><td>ST(0)</td><td>-F</td><td>or</td><td>-0</td><td>**</td><td>**</td><td>-F</td><td>or</td><td>-0</td><td>ST(0)</td><td>NaN</td></tr>
<tr><td>ST(1): -0</td><td>-0</td><td>-0</td><td>*</td><td>*</td><td>-0</td><td>-0</td><td>NaN</td></tr>
<tr><td>ST(1): +0</td><td>+0</td><td>+0</td><td>*</td><td>*</td><td>+0</td><td>+0</td><td>NaN</td></tr>
<tr><td>ST(1): +F</td><td>ST(0)</td><td>+F</td><td>or</td><td>+0</td><td>**</td><td>**</td><td>+F</td><td>or</td><td>+0</td><td>ST(0)</td><td>NaN</td></tr>
<tr><td>ST(1): +inf</td><td>*</td><td>*</td><td>*</td><td>*</td><td>*</td><td>*</td><td>NaN</td></tr>
<tr><td>ST(1): NaN</td><td>NaN</td><td>NaN</td><td>NaN</td><td>NaN</td><td>NaN</td><td>NaN</td><td>NaN</td></tr>
<tfoot>
<tr><td colspan="8">F Means finite floating-point value.</td></tr>
<tr><td colspan="8">* Indicates floating-point invalid-arithmetic-operand (#IA) exception.</td></tr>
<tr><td colspan="8">** Indicates floating-point zero-divide (#Z) exception.</td></tr>
</tfoot>
</table>
</div>
<p>When the result is 0, its sign is the same as that of the dividend. When the modulus is infinite, the result is equal to the value in ST(0).</p>
<p>The FPREM1 instruction computes the remainder specified in IEEE Standard 754. This instruction operates differently from the FPREM instruction in the way that it rounds the quotient of ST(0) divided by ST(1) to an integer (see the &quot;Operations&quot; section below).</p>
<p>Like the FPREM instruction, FPREM1 computes the remainder through iterative subtraction, but can reduce the exponent of ST(0) by no more than 63 in one execution of the instruction. If the instruction succeeds in producing a remainder that is less than one half the modulus, the operation is complete and the C2 flag in the FPU status word is cleared. Otherwise, C2 is set, and the result in ST(0) is called the partial remainder. The exponent of the partial remainder will be less than the exponent of the original dividend by at least 32. Software can re-execute the instruction (using the partial remainder in ST(0) as the dividend) until C2 is cleared. (Note that while executing such a remainder-computation loop, a higher-priority interrupting routine that needs the FPU can force a context switch in-between the instructions in the loop.) An important use of the FPREM1 instruction is to reduce the arguments of periodic functions.</p>
<p>When reduction is complete, the instruction stores the three least-significant bits of the quotient in the C3, C1, and C0 flags of the FPU status word. This information is important in argument reduction for the tangent function (using a modulus of pi/4), because it locates the original angle in the correct one of eight sectors of the unit circle.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre>D <span class="operator">=</span> GetExponent<span class="operator">(</span>ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span> <span class="operator">-</span> GetExponent<span class="operator">(</span>ST<span class="operator">(</span><span class="number">1</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
<span class="keyword">if</span><span class="operator">(</span>D <span class="operator">&lt;</span> <span class="number">64</span><span class="operator">)</span> {
	Q <span class="operator">=</span> Integer<span class="operator">(</span>RoundTowardNearestInteger<span class="operator">(</span>ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span> / ST<span class="operator">(</span><span class="number">1</span><span class="operator">)</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
	ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span> <span class="operator">=</span> ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span> <span class="operator">-</span> <span class="operator">(</span>ST<span class="operator">(</span><span class="number">1</span><span class="operator">)</span> <span class="operator">*</span> Q<span class="operator">)</span><span class="operator">;</span>
	C0 <span class="operator">=</span> GetLeastSignificantBit<span class="operator">(</span>Q2<span class="operator">)</span><span class="operator">;</span>
	C1 <span class="operator">=</span> GetLeastSignificantBit<span class="operator">(</span>Q0<span class="operator">)</span><span class="operator">;</span>
	C2 <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
	C3 <span class="operator">=</span> GetLeastSignificantBit<span class="operator">(</span>Q1<span class="operator">)</span><span class="operator">;</span>
}
<span class="keyword">else</span> {
	C2 <span class="operator">=</span> <span class="number">1</span><span class="operator">;</span>
	N <span class="operator">=</span> Constant<span class="operator">;</span> <span class="comment">//This is an implementation-dependent number between 32 and 63.</span>
	QQ <span class="operator">=</span> Integer<span class="operator">(</span>TruncateTowardZero<span class="operator">(</span><span class="operator">(</span>ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span> / ST<span class="operator">(</span><span class="number">1</span><span class="operator">)</span><span class="operator">)</span> / <span class="number">2</span><span class="operator">(</span>D <span class="operator">-</span> N<span class="operator">)</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
	ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span> <span class="operator">=</span> ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span> <span class="operator">-</span> <span class="operator">(</span>ST<span class="operator">(</span><span class="number">1</span><span class="operator">)</span> <span class="operator">*</span> QQ <span class="operator">*</span> <span class="number">2</span><span class="operator">(</span>D <span class="operator">-</span> N<span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
}
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>FPU flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>C0 Set to bit 2 (Q2) of the quotient.
C1 Set to 0 if stack underflow occurred; otherwise, set to least significant bit
of quotient (Q0).
C2 Set to 0 if reduction complete; set to 1 if incomplete.
C3 Set to bit 1 (Q1) of the quotient.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Floating-Point Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#IS</code></td><td>Stack underflow occurred.</td></tr>
<tr><td><code>#IS</code></td><td>Stack underflow occurred.</td></tr>
<tr><td><code>#IA</code></td><td>Source operand is an SNaN value, modulus (divisor) is 0, dividend is infinite, or unsupported format.</td></tr>
<tr><td><code>#D</code></td><td>Source operand is a denormal value.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
</div>
</body>
</html>

Added doc/x86/html/file_module_x86_id_109.html.































































































































































































































































































































































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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>FPTAN: Partial Tangent (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>FPTAN: Partial Tangent (x86 Instruction Set Reference)</title>
<h1>FPTAN</h1>
<h2>Partial Tangent</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>D9 F2</code></td>
<td class="grid"><code>FPTAN Replace ST(0) with its tangent and push 1 onto the FPU stack.</code></td>
<td class="grid"></td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Computes the tangent of the source operand in register ST(0), stores the result in ST(0), and pushes a 1.0 onto the FPU register stack. The source operand must be given in radians and must be less than +-2^63. The following table shows the unmasked results obtained when computing the partial tangent of various classes of numbers, assuming that underflow does not occur.</p>
<div>
<table class="grid">
<caption>FPTAN Results</caption>
<tr><th>ST(0) Source</th><th>ST(0) Destination</th></tr>
<tr><td>-inf</td><td>*</td></tr>
<tr><td>-F</td><td>-F to +F</td></tr>
<tr><td>-0</td><td>-0</td></tr>
<tr><td>+0</td><td>+0</td></tr>
<tr><td>+F</td><td>-F to +F</td></tr>
<tr><td>+inf</td><td>*</td></tr>
<tr><td>NaN</td><td>NaN</td></tr>
<tfoot>
<tr><td colspan="2">F Means finite floating-point value.</td></tr>
<tr><td colspan="2">* Indicates floating-point invalid-arithmetic-operand (#IA) exception.</td></tr>
</tfoot>
</table>
</div>
<p>If the source operand is outside the acceptable range, the C2 flag in the FPU status word is set, and the value in register ST(0) remains unchanged. The instruction does not raise an exception when the source operand is out of range. It is up to the program to check the C2 flag for out-ofrange conditions. Source values outside the range -2^63 to +2^63 can be reduced to the range of the instruction by subtracting an appropriate integer multiple of 2 * pi or by using the FPREM instruction with a divisor of 2 * pi. See the section titled &quot;Pi&quot; in Chapter 8 of the IA-32 Intel Architecture Software Developer's Manual, Volume 1, for a discussion of the proper value to use for pi in performing such reductions.</p>
<p>The value 1.0 is pushed onto the register stack after the tangent has been computed to maintain compatibility with the Intel 8087 and Intel287 math coprocessors. This operation also simplifies the calculation of other trigonometric functions. For instance, the cotangent (which is the reciprocal of the tangent) can be computed by executing a FDIVR instruction after the FPTAN instruction.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre><span class="keyword">if</span><span class="operator">(</span>ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span> <span class="operator">&lt;</span> <span class="operator">(</span><span class="number">1</span> <span class="operator">&lt;&lt;</span> <span class="number">63</span><span class="operator">)</span><span class="operator">)</span> {
	C2 <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
	ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span> <span class="operator">=</span> Tangens<span class="operator">(</span>ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
	Top <span class="operator">=</span> Top <span class="operator">-</span> <span class="number">1</span><span class="operator">;</span>
	ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span> <span class="operator">=</span> <span class="number">1.0</span><span class="operator">;</span>
}
<span class="keyword">else</span> C2 <span class="operator">=</span> <span class="number">1</span><span class="operator">;</span> <span class="comment">//source operand is out-of-range</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>FPU flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>C1 Set to 0 if stack underflow occurred; set to 1 if stack overflow occurred.
Set if result was rounded up; cleared otherwise.
C2 Set to 1 if outside range (-2^63 &lt; source operand &lt; +2^63); otherwise, set to 0.
C0, C3 Undefined.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Floating-Point Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#IS</code></td><td>Stack underflow or overflow occurred.</td></tr>
<tr><td><code>#IS</code></td><td>Stack underflow or overflow occurred.</td></tr>
<tr><td><code>#IA</code></td><td>Source operand is an SNaN value, pi, or unsupported format.</td></tr>
<tr><td><code>#D</code></td><td>Source operand is a denormal value.</td></tr>
<tr><td><code>#U</code></td><td>Result is too small for destination format.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Instruction</th>
<th>Latency</th>
<th>Throughput</th>
<th>Execution Unit</th>
</tr>
<tr><td class="grid"><code>CPUID</code></td><td class="grid">0F3n/0F2n</td><td class="grid">0F3n/0F2n</td><td class="grid">0F2n</td></tr>
<tr><td class="grid"><code>FPTAN</code></td><td class="grid">240-300/225-250</td><td class="grid">170</td><td class="grid">-</td></tr>
</table>
</object>
</div>
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>ADDSUBPS: Packed Single-FP Add/Subtract (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>ADDSUBPS: Packed Single-FP Add/Subtract (x86 Instruction Set Reference)</title>
<h1>ADDSUBPS</h1>
<h2>Packed Single-FP Add/Subtract</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>F2 0F D0 /r</code></td>
<td class="grid"><code>ADDSUBPS xmm1, xmm2/m128</code></td>
<td class="grid">Add/Subtract packed SP FP numbers from xmm2/m128 to xmm1.</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Adds odd-numbered single-precision floating-point values of the source operand (second operand) with the corresponding single-precision floating-point values from the destination operand (first operand); stores the result in the odd-numbered values of the destination operand.</p>
<p>Subtracts the even-numbered single-precision floating-point values in the source operand from the corresponding single-precision floating values in the destination operand; stores the result into the even-numbered values of the destination operand.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre>xmm1<span class="operator">[</span><span class="number">0..31</span><span class="operator">]</span> <span class="operator">=</span> xmm1<span class="operator">[</span><span class="number">0..31</span><span class="operator">]</span> <span class="operator">-</span> xmm2/m128<span class="operator">[</span><span class="number">0..31</span><span class="operator">]</span><span class="operator">;</span>
xmm1<span class="operator">[</span><span class="number">32..63</span><span class="operator">]</span> <span class="operator">=</span> xmm1<span class="operator">[</span><span class="number">32..63</span><span class="operator">]</span> <span class="operator">+</span> xmm2/m128<span class="operator">[</span><span class="number">32..63</span><span class="operator">]</span><span class="operator">;</span>
xmm1<span class="operator">[</span><span class="number">64..95</span><span class="operator">]</span> <span class="operator">=</span> xmm1<span class="operator">[</span><span class="number">64..95</span><span class="operator">]</span> <span class="operator">-</span> xmm2/m128<span class="operator">[</span><span class="number">64..95</span><span class="operator">]</span><span class="operator">;</span>
xmm1<span class="operator">[</span><span class="number">96..127</span><span class="operator">]</span> <span class="operator">=</span> xmm1<span class="operator">[</span><span class="number">96..127</span><span class="operator">]</span> <span class="operator">+</span> xmm2/m128<span class="operator">[</span><span class="number">96..127</span><span class="operator">]</span><span class="operator">;</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
When the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated.
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Numeric Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
Overflow, Underflow, Invalid, Precision, Denormal.
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#GP(0)</code></td><td>For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#SS(0)</code></td><td>For an illegal address in the SS segment.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>For a page fault.</td></tr>
<tr><td><code>#NM</code></td><td>If TS bit in CR0 is set.</td></tr>
<tr><td><code>#XM</code></td><td>For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT = 1).</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#NM</code></td><td>If TS bit in CR0 is set.</td></tr>
<tr><td><code>#XM</code></td><td>For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT = 1).</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#NM</code></td><td>If TS bit in CR0 is set.</td></tr>
<tr><td><code>#XM</code></td><td>For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT = 1).</td></tr>
<tr><td><code>#UD</code></td><td>If CR0.EM = 1. For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT = 0). If CR4.OSFXSR(bit 9) = 0. If CPUID.SSE3(ECX bit 0) = 0.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Instruction</th>
<th>Latency</th>
<th>Throughput</th>
<th>Execution Unit</th>
</tr>
<tr><td class="grid"><code>CPUID</code></td><td class="grid">0F3n</td><td class="grid">0F3n</td><td class="grid">0F3n</td></tr>
<tr><td class="grid"><code>ADDSUBPD</code></td><td class="grid">5</td><td class="grid">2</td><td class="grid">FP_ADD</td></tr>
</table>
</object>
</div>
</body>
</html>

Added doc/x86/html/file_module_x86_id_110.html.











































































































































































































































































































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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>FRNDINT: Round to Integer (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>FRNDINT: Round to Integer (x86 Instruction Set Reference)</title>
<h1>FRNDINT</h1>
<h2>Round to Integer</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>D9 FC</code></td>
<td class="grid"><code>FRNDINT</code></td>
<td class="grid">Round ST(0) to an integer.</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Rounds the source value in the ST(0) register to the nearest integral value, depending on the current rounding mode (setting of the RC field of the FPU control word), and stores the result in ST(0).</p>
<p>If the source value is infinite, the value is not changed. If the source value is not an integral value, the floating-point inexact-result exception (#P) is generated.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre>ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span> <span class="operator">=</span> RoundToIntegralValue<span class="operator">(</span>ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>FPU flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>C1 Set to 0 if stack underflow occurred.
Set if result was rounded up; cleared otherwise.
C0, C2, C3 Undefined.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Floating-Point Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#IS</code></td><td>Stack underflow occurred.</td></tr>
<tr><td><code>#IS</code></td><td>Stack underflow occurred.</td></tr>
<tr><td><code>#IA</code></td><td>Source operand is an SNaN value or unsupported format.</td></tr>
<tr><td><code>#D</code></td><td>Source operand is a denormal value.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Instruction</th>
<th>Latency</th>
<th>Throughput</th>
<th>Execution Unit</th>
</tr>
<tr><td class="grid"><code>CPUID</code></td><td class="grid">0F3n/0F2n</td><td class="grid">0F3n/0F2n</td><td class="grid">0F2n</td></tr>
<tr><td class="grid"><code>FRNDINT</code></td><td class="grid">30</td><td class="grid">11</td><td class="grid">-</td></tr>
</table>
</object>
</div>
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>FRSTOR: Restore x87 FPU State (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>FRSTOR: Restore x87 FPU State (x86 Instruction Set Reference)</title>
<h1>FRSTOR</h1>
<h2>Restore x87 FPU State</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>DD /4</code></td>
<td class="grid"><code>FRSTOR m94/108byte</code></td>
<td class="grid">Load FPU state from m94byte or m108byte.</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Loads the FPU state (operating environment and register stack) from the memory area specified with the source operand. This state data is typically written to the specified memory location by a previous FSAVE/FNSAVE instruction.</p>
<p>The FPU operating environment consists of the FPU control word, status word, tag word, instruction pointer, data pointer, and last opcode. Figures 8-9 through 8-12 in the IA-32 Intel Architecture Software Developer's Manual, Volume 1, show the layout in memory of the stored environment, depending on the operating mode of the processor (protected or real) and the current operand-size attribute (16-bit or 32-bit). In virtual-8086 mode, the real mode layouts are used. The contents of the FPU register stack are stored in the 80 bytes immediately following the operating environment image.</p>
<p>The FRSTOR instruction should be executed in the same operating mode as the corresponding FSAVE/FNSAVE instruction.</p>
<p>If one or more unmasked exception bits are set in the new FPU status word, a floating-point exception will be generated. To avoid raising exceptions when loading a new operating environment, clear all the exception flags in the FPU status word that is being loaded.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre>FPUControlWord <span class="operator">=</span> Source<span class="operator">.</span>FPUControlWord<span class="operator">;</span>
FPUStatusWord <span class="operator">=</span> Source<span class="operator">.</span>FPUStatusWord<span class="operator">.</span><span class="operator">;</span>
FPUTagWord <span class="operator">=</span> Source<span class="operator">.</span>FPUTagWord<span class="operator">.</span><span class="operator">;</span>
FPUDataPointer <span class="operator">=</span> Source<span class="operator">.</span>FPUDataPointer<span class="operator">;</span>
FPUInstructionPointer <span class="operator">=</span> Source<span class="operator">.</span>FPUInstructionPointer<span class="operator">;</span>
FPULastInstructionOpcode <span class="operator">=</span> Source<span class="operator">.</span>FPULastInstructionOpcode<span class="operator">.</span><span class="operator">;</span>
ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span> <span class="operator">=</span> Source<span class="operator">.</span>ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">;</span>
ST<span class="operator">(</span><span class="number">1</span><span class="operator">)</span> <span class="operator">=</span> Source<span class="operator">.</span>ST<span class="operator">(</span><span class="number">1</span><span class="operator">)</span><span class="operator">;</span>
ST<span class="operator">(</span><span class="number">2</span><span class="operator">)</span> <span class="operator">=</span> Source<span class="operator">.</span>ST<span class="operator">(</span><span class="number">2</span><span class="operator">)</span><span class="operator">;</span>
ST<span class="operator">(</span><span class="number">3</span><span class="operator">)</span> <span class="operator">=</span> Source<span class="operator">.</span>ST<span class="operator">(</span><span class="number">3</span><span class="operator">)</span><span class="operator">;</span>
ST<span class="operator">(</span><span class="number">4</span><span class="operator">)</span> <span class="operator">=</span> Source<span class="operator">.</span>ST<span class="operator">(</span><span class="number">4</span><span class="operator">)</span><span class="operator">;</span>
ST<span class="operator">(</span><span class="number">5</span><span class="operator">)</span> <span class="operator">=</span> Source<span class="operator">.</span>ST<span class="operator">(</span><span class="number">5</span><span class="operator">)</span><span class="operator">;</span>
ST<span class="operator">(</span><span class="number">6</span><span class="operator">)</span> <span class="operator">=</span> Source<span class="operator">.</span>ST<span class="operator">(</span><span class="number">6</span><span class="operator">)</span><span class="operator">;</span>
ST<span class="operator">(</span><span class="number">7</span><span class="operator">)</span> <span class="operator">=</span> Source<span class="operator">.</span>ST<span class="operator">(</span><span class="number">7</span><span class="operator">)</span><span class="operator">;</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>FPU flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>The C0, C1, C2, C3 flags are loaded.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Floating-Point Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>None;</code></td><td>however, this operation might unmask an existing exception that has been detected but not generated, because it was masked. Here, the exception is generated at the completion of the instruction.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#GP</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#SS</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
</div>
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>FSAVE/FNSAVE: Store x87 FPU State (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>FSAVE/FNSAVE: Store x87 FPU State (x86 Instruction Set Reference)</title>
<h1>FSAVE/FNSAVE</h1>
<h2>Store x87 FPU State</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>9B DD /6</code></td>
<td class="grid"><code>FSAVE m94/108byte</code></td>
<td class="grid">Store FPU state to m94byte or m108byte after checking for pending unmasked floating-point exceptions. Then reinitialize the FPU.</td>
</tr>
<tr>
<td class="grid"><code>DD /6</code></td>
<td class="grid"><code>FNSAVE m94/108byte</code></td>
<td class="grid">Store FPU environment to m94byte or m108byte without checking for pending unmasked floating-point exceptions. Then re-initialize the FPU. See the IA-32 Architecture Compatibility section below.</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Stores the current FPU state (operating environment and register stack) at the specified destination in memory, and then re-initializes the FPU. The FSAVE instruction checks for and handles pending unmasked floating-point exceptions before storing the FPU state; the FNSAVE instruction does not.</p>
<p>The FPU operating environment consists of the FPU control word, status word, tag word, instruction pointer, data pointer, and last opcode. Figures 8-9 through 8-12 in the IA-32 Intel Architecture Software Developer's Manual, Volume 1, show the layout in memory of the stored environment, depending on the operating mode of the processor (protected or real) and the current operand-size attribute (16-bit or 32-bit). In virtual-8086 mode, the real mode layouts are used. The contents of the FPU register stack are stored in the 80 bytes immediately follow the operating environment image.</p>
<p>The saved image reflects the state of the FPU after all floating-point instructions preceding the FSAVE/FNSAVE instruction in the instruction stream have been executed.</p>
<p>After the FPU state has been saved, the FPU is reset to the same default values it is set to with the FINIT/FNINIT instructions (see &quot;FINIT/FNINIT-Initialize Floating-Point Unit&quot; in this chapter).</p>
<p>The FSAVE/FNSAVE instructions are typically used when the operating system needs to perform a context switch, an exception handler needs to use the FPU, or an application program needs to pass a &quot;clean&quot; FPU to a procedure.</p>
<p>The assembler issues two instructions for the FSAVE instruction (an FWAIT instruction followed by an FNSAVE instruction), and the processor executes each of these instructions separately. If an exception is generated for either of these instructions, the save EIP points to the instruction that caused the exception.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre><span class="comment">//Save FPU State and Registers</span>
Destination<span class="operator">.</span>FPUControlWord <span class="operator">=</span> FPUControlWord<span class="operator">;</span>
Destination<span class="operator">.</span>FPUStatusWord <span class="operator">=</span> FPUStatusWord<span class="operator">;</span>
Destination<span class="operator">.</span>FPUTagWord <span class="operator">=</span> FPUTagWord<span class="operator">;</span>
Destination<span class="operator">.</span>FPUDataPointer <span class="operator">=</span> FPUDataPointer<span class="operator">;</span>
Destination<span class="operator">.</span>FPUInstructionPointer <span class="operator">=</span> FPUInstructionPointer<span class="operator">;</span>
Destination<span class="operator">.</span>FPULastInstructionOpcode <span class="operator">=</span> FPULastInstructionOpcode<span class="operator">;</span>
Destination<span class="operator">.</span>ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span> <span class="operator">=</span> ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">;</span>
Destination<span class="operator">.</span>ST<span class="operator">(</span><span class="number">1</span><span class="operator">)</span> <span class="operator">=</span> ST<span class="operator">(</span><span class="number">1</span><span class="operator">)</span><span class="operator">;</span>
Destination<span class="operator">.</span>ST<span class="operator">(</span><span class="number">2</span><span class="operator">)</span> <span class="operator">=</span> ST<span class="operator">(</span><span class="number">2</span><span class="operator">)</span><span class="operator">;</span>
Destination<span class="operator">.</span>ST<span class="operator">(</span><span class="number">3</span><span class="operator">)</span> <span class="operator">=</span> ST<span class="operator">(</span><span class="number">3</span><span class="operator">)</span><span class="operator">;</span>
Destination<span class="operator">.</span>ST<span class="operator">(</span><span class="number">4</span><span class="operator">)</span> <span class="operator">=</span> ST<span class="operator">(</span><span class="number">4</span><span class="operator">)</span><span class="operator">;</span>
Destination<span class="operator">.</span>ST<span class="operator">(</span><span class="number">5</span><span class="operator">)</span> <span class="operator">=</span> ST<span class="operator">(</span><span class="number">5</span><span class="operator">)</span><span class="operator">;</span>
Destination<span class="operator">.</span>ST<span class="operator">(</span><span class="number">6</span><span class="operator">)</span> <span class="operator">=</span> ST<span class="operator">(</span><span class="number">6</span><span class="operator">)</span><span class="operator">;</span>
Destination<span class="operator">.</span>ST<span class="operator">(</span><span class="number">7</span><span class="operator">)</span> <span class="operator">=</span> ST<span class="operator">(</span><span class="number">7</span><span class="operator">)</span><span class="operator">;</span>
<span class="comment">//Initialize FPU</span>
FPUControlWord <span class="operator">=</span> <span class="number">0x37F</span><span class="operator">;</span>
FPUStatusWord <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
FPUTagWord <span class="operator">=</span> <span class="number">0xFFFF</span><span class="operator">;</span>
FPUDataPointer <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
FPUInstructionPointer <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
FPULastInstructionOpcode <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>FPU flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>The C0, C1, C2, and C3 flags are saved and then cleared.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>IA-32 Architecture Compatibility</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>For Intel math coprocessors and FPUs prior to the Intel Pentium processor, an FWAIT instruction should be executed before attempting to read from the memory image stored with a prior FSAVE/FNSAVE instruction. This FWAIT instruction helps insure that the storage operation has been completed.
When operating a Pentium or Intel486 processor in MS-DOS compatibility mode, it is possible (under unusual circumstances) for an FNSAVE instruction to be interrupted prior to being executed to handle a pending FPU exception. See the section titled &quot;No-Wait FPU Instructions Can Get FPU Interrupt in Window&quot; in Appendix D of the IA-32 Intel Architecture Software Developer's Manual, Volume 1, for a description of these circumstances. An FNSAVE instruction cannot be interrupted in this way on a Pentium 4, Intel Xeon, or P6 family processor.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Floating-Point Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
None.
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#GP</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#SS</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
</div>
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>FSCALE: Scale (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>FSCALE: Scale (x86 Instruction Set Reference)</title>
<h1>FSCALE</h1>
<h2>Scale</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>D9 FD</code></td>
<td class="grid"><code>FSCALE</code></td>
<td class="grid">Scale ST(0) by ST(1).</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Truncates the value in the source operand (toward 0) to an integral value and adds that value to the exponent of the destination operand. The destination and source operands are floating-point values located in registers ST(0) and ST(1), respectively. This instruction provides rapid multiplication or division by integral powers of 2. The following table shows the results obtained when scaling various classes of numbers, assuming that neither overflow nor underflow occurs.</p>
<div>
<table class="grid">
<caption>FSCALE Results</caption>
<tr><td>-</td><td>ST(1): -inf</td><td>ST(1): -F</td><td>ST(1): -0</td><td>ST(1): +0</td><td>ST(1): +F</td><td>ST(1): +inf</td><td>ST(1): NaN</td></tr>
<tr><td>ST(0): -inf</td><td>NaN</td><td>-inf</td><td>-inf</td><td>-inf</td><td>-inf</td><td>-inf</td><td>NaN</td></tr>
<tr><td>ST(0): -F</td><td>-0</td><td>-F</td><td>-F</td><td>-F</td><td>-F</td><td>-inf</td><td>NaN</td></tr>
<tr><td>ST(0): -0</td><td>-0</td><td>-0</td><td>-0</td><td>-0</td><td>-0</td><td>NaN</td><td>NaN</td></tr>
<tr><td>ST(0): +0</td><td>+0</td><td>+0</td><td>+0</td><td>+0</td><td>+0</td><td>NaN</td><td>NaN</td></tr>
<tr><td>ST(0): +F</td><td>+0</td><td>+F</td><td>+F</td><td>+F</td><td>+F</td><td>+inf</td><td>NaN</td></tr>
<tr><td>ST(0): +inf</td><td>NaN</td><td>+inf</td><td>+inf</td><td>+inf</td><td>+inf</td><td>+inf</td><td>NaN</td></tr>
<tr><td>ST(0): NaN</td><td>NaN</td><td>NaN</td><td>NaN</td><td>NaN</td><td>NaN</td><td>NaN</td><td>NaN</td></tr>
<tfoot>
<tr><td colspan="8">F Means finite floating-point value.</td></tr>
</tfoot>
</table>
</div>
<p>In most cases, only the exponent is changed and the mantissa remains unchanged.</p>
<p>However, when the value being scaled in ST(0) is a denormal value, the mantissa is also changed and the result may turn out to be a normalized number. Similarly, if overflow or underflow results from a scale operation, the resulting mantissa will differ from the source's mantissa.</p>
<p>The FSCALE instruction can also be used to reverse the action of the FXTRACT instruction, as shown in the following example: FXTRACT; FSCALE; FSTP ST(1); In this example, the FXTRACT instruction extracts the mantissa and exponent from the value in ST(0) and stores them in ST(0) and ST(1) respectively. The FSCALE then scales the mantissa in ST(0) by the exponent in ST(1), recreating the original value before the FXTRACT operation was performed. The FSTP ST(1) instruction overwrites the exponent (extracted by the FXTRACT instruction) with the recreated value, which returns the stack to its original state with only one register [ST(0)] occupied.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre>ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span> <span class="operator">=</span> ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span> <span class="operator">*</span> <span class="number">2</span>RoundTowardZero<span class="operator">(</span>ST<span class="operator">(</span><span class="number">1</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>FPU flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>C1 Set to 0 if stack underflow occurred.
Set if result was rounded up; cleared otherwise.
C0, C2, C3 Undefined.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Floating-Point Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#IS</code></td><td>Stack underflow occurred.</td></tr>
<tr><td><code>#IS</code></td><td>Stack underflow occurred.</td></tr>
<tr><td><code>#IA</code></td><td>Source operand is an SNaN value or unsupported format.</td></tr>
<tr><td><code>#D</code></td><td>Source operand is a denormal value.</td></tr>
<tr><td><code>#U</code></td><td>Result is too small for destination format.</td></tr>
<tr><td><code>#O</code></td><td>Result is too large for destination format.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Instruction</th>
<th>Latency</th>
<th>Throughput</th>
<th>Execution Unit</th>
</tr>
<tr><td class="grid"><code>CPUID</code></td><td class="grid">0F3n/0F2n</td><td class="grid">0F3n/0F2n</td><td class="grid">0F2n</td></tr>
<tr><td class="grid"><code>FSCALE</code></td><td class="grid">60</td><td class="grid">7</td><td class="grid">-</td></tr>
</table>
</object>
</div>
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>FSIN: Sine (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>FSIN: Sine (x86 Instruction Set Reference)</title>
<h1>FSIN</h1>
<h2>Sine</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>D9 FE</code></td>
<td class="grid"><code>FSIN</code></td>
<td class="grid">Replace ST(0) with its sine.</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Computes the sine of the source operand in register ST(0) and stores the result in ST(0). The source operand must be given in radians and must be within the range -2^63 to +2^63. The following table shows the results obtained when taking the sine of various classes of numbers, assuming that underflow does not occur.</p>
<div>
<table class="grid">
<caption>FSIN Results</caption>
<tr><th>Source (ST(0))</th><th>Destination (ST(0))</th></tr>
<tr><td>-inf</td><td>*</td></tr>
<tr><td>-F</td><td>-1 to +1</td></tr>
<tr><td>-0</td><td>-0</td></tr>
<tr><td>+0</td><td>+0</td></tr>
<tr><td>+F</td><td>-1 to +1</td></tr>
<tr><td>+inf</td><td>*</td></tr>
<tr><td>NaN</td><td>NaN</td></tr>
<tfoot>
<tr><td colspan="2">F Means finite floating-point value.</td></tr>
<tr><td colspan="2">* Indicates floating-point invalid-arithmetic-operand (#IA) exception.</td></tr>
</tfoot>
</table>
</div>
<p>If the source operand is outside the acceptable range, the C2 flag in the FPU status word is set, and the value in register ST(0) remains unchanged. The instruction does not raise an exception when the source operand is out of range. It is up to the program to check the C2 flag for out-ofrange conditions. Source values outside the range -2^63 to +2^63 can be reduced to the range of the instruction by subtracting an appropriate integer multiple of 2Pi or by using the FPREM instruction with a divisor of 2Pi. See the section titled &quot;Pi&quot; in Chapter 8 of the IA-32 Intel Architecture Software Developer's Manual, Volume 1, for a discussion of the proper value to use for pi in performing such reductions.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre><span class="keyword">if</span><span class="operator">(</span>ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span> <span class="operator">&lt;</span> <span class="operator">(</span><span class="number">1</span> <span class="operator">&lt;&lt;</span> <span class="number">63</span><span class="operator">)</span><span class="operator">)</span> {
	C2 <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
	ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span> <span class="operator">=</span> Sine<span class="operator">(</span>ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
}
<span class="keyword">else</span> C2 <span class="operator">=</span> <span class="number">1</span><span class="operator">;</span> <span class="comment">//source operand out of range</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>FPU flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>C1 Set to 0 if stack underflow occurred.
Set if result was rounded up; cleared otherwise.
C2 Set to 1 if outside range (-2^63 &lt; source operand &lt; +2^63); otherwise, set to 0.
C0, C3 Undefined.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Floating-Point Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#IS</code></td><td>Stack underflow occurred.</td></tr>
<tr><td><code>#IS</code></td><td>Stack underflow occurred.</td></tr>
<tr><td><code>#IA</code></td><td>Source operand is an SNaN value, infinite, or unsupported format.</td></tr>
<tr><td><code>#D</code></td><td>Source operand is a denormal value.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Instruction</th>
<th>Latency</th>
<th>Throughput</th>
<th>Execution Unit</th>
</tr>
<tr><td class="grid"><code>CPUID</code></td><td class="grid">0F3n/0F2n</td><td class="grid">0F3n/0F2n</td><td class="grid">0F2n</td></tr>
<tr><td class="grid"><code>FSIN</code></td><td class="grid">160-200/160-180</td><td class="grid">130</td><td class="grid">-</td></tr>
</table>
</object>
</div>
</body>
</html>

Added doc/x86/html/file_module_x86_id_115.html.































































































































































































































































































































































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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>FSINCOS: Sine and Cosine (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>FSINCOS: Sine and Cosine (x86 Instruction Set Reference)</title>
<h1>FSINCOS</h1>
<h2>Sine and Cosine</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>D9 FB</code></td>
<td class="grid"><code>FSINCOS</code></td>
<td class="grid">Compute the sine and cosine of ST(0); replace ST(0) with the sine, and push the cosine onto the register stack.</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Computes both the sine and the cosine of the source operand in register ST(0), stores the sine in ST(0), and pushes the cosine onto the top of the FPU register stack. (This instruction is faster than executing the FSIN and FCOS instructions in succession.) The source operand must be given in radians and must be within the range -2^63 to +2^63. The following table shows the results obtained when taking the sine and cosine of various classes of numbers, assuming that underflow does not occur.</p>
<div>
<table class="grid">
<caption>FSINCOS results</caption>
<tr><th>Source: ST(0)</th><th>Destination: ST(1) Cosine</th><th>Destination: ST(0) Sine</th></tr>
<tr><td>-inf</td><td>*</td><td>*</td></tr>
<tr><td>-F</td><td>-1 to +1</td><td>-1 to +1</td></tr>
<tr><td>-0</td><td>+1</td><td>-0</td></tr>
<tr><td>+0</td><td>+1</td><td>+0</td></tr>
<tr><td>+F</td><td>-1 to +1</td><td>-1 to +1</td></tr>
<tr><td>+inf</td><td>*</td><td>*</td></tr>
<tr><td>NaN</td><td>NaN</td><td>NaN</td></tr>
<tfoot>
<tr><td colspan="3">F Means finite floating-point value.</td></tr>
<tr><td colspan="3">* Indicates floating-point invalid-arithmetic-operand (#IA) exception.</td></tr>
</tfoot>
</table>
</div>
<p>If the source operand is outside the acceptable range, the C2 flag in the FPU status word is set, and the value in register ST(0) remains unchanged. The instruction does not raise an exception when the source operand is out of range. It is up to the program to check the C2 flag for out-ofrange conditions. Source values outside the range -2^63 to +2^63 can be reduced to the range of the instruction by subtracting an appropriate integer multiple of 2Pi or by using the FPREM instruction with a divisor of 2Pi. See the section titled &quot;Pi&quot; in Chapter 8 of the IA-32 Intel Architecture Software Developer's Manual, Volume 1, for a discussion of the proper value to use for pi in performing such reductions.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre><span class="keyword">if</span><span class="operator">(</span>ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span> <span class="operator">&lt;</span> <span class="operator">(</span><span class="number">1</span> <span class="operator">&lt;&lt;</span> <span class="number">63</span><span class="operator">)</span><span class="operator">)</span> {
	C2 <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
	Temporary <span class="operator">=</span> Cosine<span class="operator">(</span>ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
	ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span> <span class="operator">=</span> Sine<span class="operator">(</span>ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
	Top <span class="operator">=</span> Top <span class="operator">-</span> <span class="number">1</span><span class="operator">;</span>
	ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span> <span class="operator">=</span> Temporary<span class="operator">;</span>
}
<span class="keyword">else</span> C2 <span class="operator">=</span> <span class="number">1</span><span class="operator">;</span> <span class="comment">//source operand out of range</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>FPU flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>C1 Set to 0 if stack underflow occurred; set to 1 of stack overflow occurs.
Set if result was rounded up; cleared otherwise.
C2 Set to 1 if outside range (-2^63 &lt; source operand &lt; +2^63); otherwise, set to 0.
C0, C3 Undefined.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Floating-Point Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#IS</code></td><td>Stack underflow or overflow occurred.</td></tr>
<tr><td><code>#IS</code></td><td>Stack underflow or overflow occurred.</td></tr>
<tr><td><code>#IA</code></td><td>Source operand is an SNaN value, infinite, or unsupported format.</td></tr>
<tr><td><code>#D</code></td><td>Source operand is a denormal value.</td></tr>
<tr><td><code>#U</code></td><td>Result is too small for destination format.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Instruction</th>
<th>Latency</th>
<th>Throughput</th>
<th>Execution Unit</th>
</tr>
<tr><td class="grid"><code>CPUID</code></td><td class="grid">0F3n/0F2n</td><td class="grid">0F3n/0F2n</td><td class="grid">0F2n</td></tr>
<tr><td class="grid"><code>FSINCOS</code></td><td class="grid">170-250/160-220</td><td class="grid">140</td><td class="grid">-</td></tr>
</table>
</object>
</div>
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>FSQRT: Square Root (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>FSQRT: Square Root (x86 Instruction Set Reference)</title>
<h1>FSQRT</h1>
<h2>Square Root</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>D9 FA</code></td>
<td class="grid"><code>FSQRT</code></td>
<td class="grid">Computes square root of ST(0) and stores the result in ST(0).</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Computes the square root of the source value in the ST(0) register and stores the result in ST(0).</p>
<p>The following table shows the results obtained when taking the square root of various classes of numbers, assuming that neither overflow nor underflow occurs.</p>
<div>
<table class="grid">
<caption>FSQRT Results</caption>
<tr><th>Source (ST(0))</th><th>Destination (ST(0))</th></tr>
<tr><td>-inf</td><td>*</td></tr>
<tr><td>-F</td><td>*</td></tr>
<tr><td>-0</td><td>-0</td></tr>
<tr><td>+0</td><td>+0</td></tr>
<tr><td>+F</td><td>+F</td></tr>
<tr><td>+inf</td><td>+inf</td></tr>
<tr><td>NaN</td><td>NaN</td></tr>
<tfoot>
<tr><td colspan="2">F Means finite floating-point value.</td></tr>
<tr><td colspan="2">* Indicates floating-point invalid-arithmetic-operand (#IA) exception.</td></tr>
</tfoot>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre>ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span> <span class="operator">=</span> SquareRoot<span class="operator">(</span>ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>FPU flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>C1 Set to 0 if stack underflow occurred.
Set if result was rounded up; cleared otherwise.
C0, C2, C3 Undefined.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Floating-Point Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#IS</code></td><td>Stack underflow occurred.</td></tr>
<tr><td><code>#IS</code></td><td>Stack underflow occurred.</td></tr>
<tr><td><code>#IA</code></td><td>Source operand is an SNaN value or unsupported format. Source operand is a negative value (except for -0).</td></tr>
<tr><td><code>#D</code></td><td>Source operand is a denormal value.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Instruction</th>
<th>Latency</th>
<th>Throughput</th>
<th>Execution Unit</th>
</tr>
<tr><td class="grid"><code>CPUID</code></td><td class="grid">0F3n/0F2n</td><td class="grid">0F3n/0F2n</td><td class="grid">0F2n</td></tr>
<tr><td class="grid"><code>FSQRT SP</code></td><td class="grid">30/23</td><td class="grid">30/23</td><td class="grid">FP_DIV</td></tr>
<tr><td class="grid"><code>FSQRT DP</code></td><td class="grid">40/38</td><td class="grid">40/38</td><td class="grid">FP_DIV</td></tr>
<tr><td class="grid"><code>FSQRT EP</code></td><td class="grid">44/43</td><td class="grid">44/43</td><td class="grid">FP_DIV</td></tr>
</table>
</object>
</div>
</body>
</html>

Added doc/x86/html/file_module_x86_id_117.html.

















































































































































































































































































































































































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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>FST/FSTP: Store Floating Point Value (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>FST/FSTP: Store Floating Point Value (x86 Instruction Set Reference)</title>
<h1>FST/FSTP</h1>
<h2>Store Floating Point Value</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>D9 /2</code></td>
<td class="grid"><code>FST m32fp</code></td>
<td class="grid">Copy ST(0) to m32fp.</td>
</tr>
<tr>
<td class="grid"><code>DD /2</code></td>
<td class="grid"><code>FST m64fp</code></td>
<td class="grid">Copy ST(0) to m64fp.</td>
</tr>
<tr>
<td class="grid"><code>DD D0+i</code></td>
<td class="grid"><code>FST ST(i)</code></td>
<td class="grid">Copy ST(0) to ST(i).</td>
</tr>
<tr>
<td class="grid"><code>D9 /3</code></td>
<td class="grid"><code>FSTP m32fp</code></td>
<td class="grid">Copy ST(0) to m32fp and pop register stack.</td>
</tr>
<tr>
<td class="grid"><code>DD /3</code></td>
<td class="grid"><code>FSTP m64fp</code></td>
<td class="grid">Copy ST(0) to m64fp and pop register stack.</td>
</tr>
<tr>
<td class="grid"><code>DB /7</code></td>
<td class="grid"><code>FSTP m80fp</code></td>
<td class="grid">Copy ST(0) to m80fp and pop register stack.</td>
</tr>
<tr>
<td class="grid"><code>DD D8+i</code></td>
<td class="grid"><code>FSTP ST(i)</code></td>
<td class="grid">Copy ST(0) to ST(i) and pop register stack.</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>The FST instruction copies the value in the ST(0) register to the destination operand, which can be a memory location or another register in the FPU register stack. When storing the value in memory, the value is converted to single-precision or double-precision floating-point format.</p>
<p>The FSTP instruction performs the same operation as the FST instruction and then pops the register stack. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1. The FSTP instruction can also store values in memory in double extended-precision floating-point format.</p>
<p>If the destination operand is a memory location, the operand specifies the address where the first byte of the destination value is to be stored. If the destination operand is a register, the operand specifies a register in the register stack relative to the top of the stack.</p>
<p>If the destination size is single-precision or double-precision, the mantissa of the value being stored is rounded to the width of the destination (according to the rounding mode specified by the RC field of the FPU control word), and the exponent is converted to the width and bias of the destination format. If the value being stored is too large for the destination format, a numeric overflow exception (#O) is generated and, if the exception is unmasked, no value is stored in the destination operand. If the value being stored is a denormal value, the denormal exception (#D) is not generated. This condition is simply signaled as a numeric underflow exception (#U) condition.</p>
<p>If the value being stored is +-0, +-infinite, or a NaN, the least-significant bits of the mantissa and the exponent are truncated to fit the destination format. This operation preserves the value's identity as a 0, infinite, or NaN.</p>
<p>If the destination operand is a non-empty register, the invalid-operation exception is not generated.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre>Destination <span class="operator">=</span> ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">;</span>
<span class="keyword">if</span><span class="operator">(</span>Instruction <span class="operator">==</span> FSTP<span class="operator">)</span> PopRegisterStack<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>FPU flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>C1 Set to 0 if stack underflow occurred.
Indicates rounding direction of if the floating-point inexact exception (#P)
is generated: 0 = not roundup; 1 = roundup.
C0, C2, C3 Undefined.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Floating-Point Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#IS</code></td><td>Stack underflow occurred.</td></tr>
<tr><td><code>#IS</code></td><td>Stack underflow occurred.</td></tr>
<tr><td><code>#IA</code></td><td>Source operand is an SNaN value or unsupported format. Does not occur if the source operand is in double extended-precision floating-point format.</td></tr>
<tr><td><code>#U</code></td><td>Result is too small for the destination format.</td></tr>
<tr><td><code>#O</code></td><td>Result is too large for the destination format.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#GP</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#SS</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
</div>
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>FSTCW/FNSTCW: Store x87 FPU Control Word (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>FSTCW/FNSTCW: Store x87 FPU Control Word (x86 Instruction Set Reference)</title>
<h1>FSTCW/FNSTCW</h1>
<h2>Store x87 FPU Control Word</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>9B D9 /7</code></td>
<td class="grid"><code>FSTCW m2byte</code></td>
<td class="grid">Store FPU control word to m2byte after checking for pending unmasked floating-point exceptions.</td>
</tr>
<tr>
<td class="grid"><code>D9 /7</code></td>
<td class="grid"><code>FNSTCW m2byte</code></td>
<td class="grid">Store FPU control word to m2byte without checking for pending unmasked floating-point exceptions. See IA-32 Architecture Compatibility section below.</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Stores the current value of the FPU control word at the specified destination in memory. The FSTCW instruction checks for and handles pending unmasked floating-point exceptions before storing the control word; the FNSTCW instruction does not.</p>
<p>The assembler issues two instructions for the FSTCW instruction (an FWAIT instruction followed by an FNSTCW instruction), and the processor executes each of these instructions in separately. If an exception is generated for either of these instructions, the save EIP points to the instruction that caused the exception.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre>Destination <span class="operator">=</span> FPUControlWord<span class="operator">;</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>FPU flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>The C0, C1, C2, and C3 flags are undefined.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>IA-32 Architecture Compatibility</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>When operating a Pentium or Intel486 processor in MS-DOS compatibility mode, it is possible (under unusual circumstances) for an FNSTCW instruction to be interrupted prior to being executed to handle a pending FPU exception. See the section titled &quot;No-Wait FPU Instructions Can Get FPU Interrupt in Window&quot; in Appendix D of the IA-32 Intel Architecture Software Developer's Manual, Volume 1, for a description of these circumstances. An FNSTCW instruction cannot be interrupted in this way on a Pentium 4, Intel Xeon, or P6 family processor.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Floating-Point Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
None.
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#GP</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#SS</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
</div>
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>FSTENV/FNSTENV: Store x87 FPU Environment (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>FSTENV/FNSTENV: Store x87 FPU Environment (x86 Instruction Set Reference)</title>
<h1>FSTENV/FNSTENV</h1>
<h2>Store x87 FPU Environment</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>9B D9 /6</code></td>
<td class="grid"><code>FSTENV m14/28byte</code></td>
<td class="grid">Store FPU environment to m14byte or m28byte after checking for pending unmasked floating-point exceptions. Then mask all floating-point exceptions.</td>
</tr>
<tr>
<td class="grid"><code>D9 /6</code></td>
<td class="grid"><code>FNSTENV* m14/28byte</code></td>
<td class="grid">Store FPU environment to m14byte or m28byte without checking for pending unmasked floating-point exceptions. Then mask all floating-point exceptions. See the IA-32 Architecture Compatibility section below.</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Saves the current FPU operating environment at the memory location specified with the destination operand, and then masks all floating-point exceptions. The FPU operating environment consists of the FPU control word, status word, tag word, instruction pointer, data pointer, and last opcode. Figures 8-9 through 8-12 in the IA-32 Intel Architecture Software Developer's Manual, Volume 1, show the layout in memory of the stored environment, depending on the operating mode of the processor (protected or real) and the current operand-size attribute (16- bit or 32-bit). In virtual-8086 mode, the real mode layouts are used.</p>
<p>The FSTENV instruction checks for and handles any pending unmasked floating-point exceptions before storing the FPU environment; the FNSTENV instruction does not. The saved image reflects the state of the FPU after all floating-point instructions preceding the FSTENV/FNSTENV instruction in the instruction stream have been executed.</p>
<p>These instructions are often used by exception handlers because they provide access to the FPU instruction and data pointers. The environment is typically saved in the stack. Masking all exceptions after saving the environment prevents floating-point exceptions from interrupting the exception handler.</p>
<p>The assembler issues two instructions for the FSTENV instruction (an FWAIT instruction followed by an FNSTENV instruction), and the processor executes each of these instructions separately. If an exception is generated for either of these instructions, the save EIP points to the instruction that caused the exception.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre>Destination<span class="operator">.</span>FPUControlWord <span class="operator">=</span> FPUControlWord<span class="operator">;</span>
Destination<span class="operator">.</span>FPUStatusWord <span class="operator">=</span> FPUStatusWord<span class="operator">;</span>
Destination<span class="operator">.</span>FPUTagWord <span class="operator">=</span> FPUTagWord<span class="operator">;</span>
Destination<span class="operator">.</span>FPUDataPointer <span class="operator">=</span> FPUDataPointer<span class="operator">;</span>
Destination<span class="operator">.</span>FPUInstructionPointer <span class="operator">=</span> FPUInstructionPointer<span class="operator">;</span>
Destination<span class="operator">.</span>FPULastInstructionOpcode <span class="operator">=</span> FPULastInstructionOpcode<span class="operator">;</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>FPU flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>The C0, C1, C2, and C3 are undefined.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>IA-32 Architecture Compatibility</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>When operating a Pentium or Intel486 processor in MS-DOS compatibility mode, it is possible (under unusual circumstances) for an FNSTENV instruction to be interrupted prior to being executed to handle a pending FPU exception. See the section titled &quot;No-Wait FPU Instructions Can Get FPU Interrupt in Window&quot; in Appendix D of the IA-32 Intel Architecture Software Developer's Manual, Volume 1, for a description of these circumstances. An FNSTENV instruction cannot be interrupted in this way on a Pentium 4, Intel Xeon, or P6 family processor.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Floating-Point Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
None.
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#GP</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#SS</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
</div>
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>AND: Logical AND (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>AND: Logical AND (x86 Instruction Set Reference)</title>
<h1>AND</h1>
<h2>Logical AND</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>24 ib</code></td>
<td class="grid"><code>AND AL, imm8</code></td>
<td class="grid">AL AND imm8</td>
</tr>
<tr>
<td class="grid"><code>25 iw</code></td>
<td class="grid"><code>AND AX, imm16</code></td>
<td class="grid">AX AND imm16</td>
</tr>
<tr>
<td class="grid"><code>25 id</code></td>
<td class="grid"><code>AND EAX, imm32</code></td>
<td class="grid">EAX AND imm32</td>
</tr>
<tr>
<td class="grid"><code>80 /4 ib</code></td>
<td class="grid"><code>AND r/m8, imm8</code></td>
<td class="grid">r/m8 AND imm8</td>
</tr>
<tr>
<td class="grid"><code>81 /4 iw</code></td>
<td class="grid"><code>AND r/m16, imm16</code></td>
<td class="grid">r/m16 AND imm16</td>
</tr>
<tr>
<td class="grid"><code>81 /4 id</code></td>
<td class="grid"><code>AND r/m32, imm32</code></td>
<td class="grid">r/m32 AND imm32</td>
</tr>
<tr>
<td class="grid"><code>83 /4 ib</code></td>
<td class="grid"><code>AND r/m16, imm8</code></td>
<td class="grid">r/m16 AND imm8 (sign-extended)</td>
</tr>
<tr>
<td class="grid"><code>83 /4 ib</code></td>
<td class="grid"><code>AND r/m32, imm8</code></td>
<td class="grid">r/m32 AND imm8 (sign-extended)</td>
</tr>
<tr>
<td class="grid"><code>20 /r</code></td>
<td class="grid"><code>AND r/m8, r8</code></td>
<td class="grid">r/m8 AND r8</td>
</tr>
<tr>
<td class="grid"><code>21 /r</code></td>
<td class="grid"><code>AND r/m16, r16</code></td>
<td class="grid">r/m16 AND r16</td>
</tr>
<tr>
<td class="grid"><code>21 /r</code></td>
<td class="grid"><code>AND r/m32, r32</code></td>
<td class="grid">r/m32 AND r32</td>
</tr>
<tr>
<td class="grid"><code>22 /r</code></td>
<td class="grid"><code>AND r8, r/m8</code></td>
<td class="grid">r8 AND r/m8</td>
</tr>
<tr>
<td class="grid"><code>23 /r</code></td>
<td class="grid"><code>AND r16, r/m16</code></td>
<td class="grid">r16 AND r/m16</td>
</tr>
<tr>
<td class="grid"><code>23 /r</code></td>
<td class="grid"><code>AND r32, r/m32</code></td>
<td class="grid">r32 AND r/m32</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Performs a bitwise AND operation on the destination (first) and source (second) operands and stores the result in the destination operand location. The source operand can be an immediate, a register, or a memory location; the destination operand can be a register or a memory location.</p>
<p>(However, two memory operands cannot be used in one instruction.) Each bit of the result is set to 1 if both corresponding bits of the first and second operands are 1; otherwise, it is set to 0.</p>
<p>This instruction can be used with a LOCK prefix to allow the it to be executed atomically.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre>Destination <span class="operator">=</span> Destination <span class="operator">&amp;</span> Source<span class="operator">;</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>The OF and CF flags are cleared; the SF, ZF, and PF flags are set according to the result. The state of the AF flag is undefined.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If the destination operand points to a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a null segment selector.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If the destination operand points to a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register contains a null segment selector.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#GP</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Instruction</th>
<th>Latency</th>
<th>Throughput</th>
<th>Execution Unit</th>
</tr>
<tr><td class="grid"><code>CPUID</code></td><td class="grid">0F3n/0F2n</td><td class="grid">0F3n/0F2n</td><td class="grid">0F2n</td></tr>
<tr><td class="grid"><code>AND</code></td><td class="grid">1/0.5</td><td class="grid">0.5/0.5</td><td class="grid">ALU</td></tr>
</table>
</object>
</div>
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>FSTSW/FNSTSW: Store x87 FPU Status Word (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>FSTSW/FNSTSW: Store x87 FPU Status Word (x86 Instruction Set Reference)</title>
<h1>FSTSW/FNSTSW</h1>
<h2>Store x87 FPU Status Word</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>9B DD /7</code></td>
<td class="grid"><code>FSTSW m2byte</code></td>
<td class="grid">Store FPU status word at m2byte after checking for pending unmasked floating-point exceptions.</td>
</tr>
<tr>
<td class="grid"><code>9B DF E0</code></td>
<td class="grid"><code>FSTSW AX</code></td>
<td class="grid">Store FPU status word in AX register after checking for pending unmasked floating-point exceptions.</td>
</tr>
<tr>
<td class="grid"><code>DD /7</code></td>
<td class="grid"><code>FNSTSW* m2byte</code></td>
<td class="grid">Store FPU status word at m2byte without checking for pending unmasked floating-point exceptions.</td>
</tr>
<tr>
<td class="grid"><code>DF E0</code></td>
<td class="grid"><code>FNSTSW* AX</code></td>
<td class="grid">Store FPU status word in AX register without checking for pending unmasked floating-point exceptions.</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>NOTE: * See IA-32 Architecture Compatibility section below.</p>
<p>Stores the current value of the x87 FPU status word in the destination location. The destination operand can be either a two-byte memory location or the AX register. The FSTSW instruction checks for and handles pending unmasked floating-point exceptions before storing the status word; the FNSTSW instruction does not.</p>
<p>The FNSTSW AX form of the instruction is used primarily in conditional branching (for instance, after an FPU comparison instruction or an FPREM, FPREM1, or FXAM instruction), where the direction of the branch depends on the state of the FPU condition code flags. (See the section titled &quot;Branching and Conditional Moves on FPU Condition Codes&quot; in Chapter 8 of the IA-32 Intel Architecture Software Developer's Manual, Volume 1.) This instruction can also be used to invoke exception handlers (by examining the exception flags) in environments that do not use interrupts. When the FNSTSW AX instruction is executed, the AX register is updated before the processor executes any further instructions. The status stored in the AX register is thus guaranteed to be from the completion of the prior FPU instruction.</p>
<p>The assembler issues two instructions for the FSTSW instruction (an FWAIT instruction followed by an FNSTSW instruction), and the processor executes each of these instructions separately. If an exception is generated for either of these instructions, the save EIP points to the instruction that caused the exception.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre>Destination <span class="operator">=</span> FPUStatusWord<span class="operator">;</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>FPU flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>The C0, C1, C2, and C3 are undefined.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>IA-32 Architecture Compatibility</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>When operating a Pentium or Intel486 processor in MS-DOS compatibility mode, it is possible (under unusual circumstances) for an FNSTSW instruction to be interrupted prior to being executed to handle a pending FPU exception. See the section titled &quot;No-Wait FPU Instructions Can Get FPU Interrupt in Window&quot; in Appendix D of the IA-32 Intel Architecture Software Developer's Manual, Volume 1, for a description of these circumstances. An FNSTSW instruction cannot be interrupted in this way on a Pentium 4, Intel Xeon, or P6 family processor.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Floating-Point Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
None.
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If the destination is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#GP</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#SS</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
</div>
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>FSUB/FSUBP/FISUB: Subtract (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>FSUB/FSUBP/FISUB: Subtract (x86 Instruction Set Reference)</title>
<h1>FSUB/FSUBP/FISUB</h1>
<h2>Subtract</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>D8 /4</code></td>
<td class="grid"><code>FSUB m32fp</code></td>
<td class="grid">Subtract m32fp from ST(0) and store result in ST(0).</td>
</tr>
<tr>
<td class="grid"><code>DC /4</code></td>
<td class="grid"><code>FSUB m64fp</code></td>
<td class="grid">Subtract m64fp from ST(0) and store result in ST(0).</td>
</tr>
<tr>
<td class="grid"><code>D8 E0+i</code></td>
<td class="grid"><code>FSUB ST(0), ST(i)</code></td>
<td class="grid">Subtract ST(i) from ST(0) and store result in ST(0).</td>
</tr>
<tr>
<td class="grid"><code>DC E8+i</code></td>
<td class="grid"><code>FSUB ST(i), ST(0)</code></td>
<td class="grid">Subtract ST(0) from ST(i) and store result in ST(i).</td>
</tr>
<tr>
<td class="grid"><code>DE E8+i</code></td>
<td class="grid"><code>FSUBP ST(i), ST(0)</code></td>
<td class="grid">Subtract ST(0) from ST(i), store result in ST(i), and pop register stack.</td>
</tr>
<tr>
<td class="grid"><code>DE E9</code></td>
<td class="grid"><code>FSUBP</code></td>
<td class="grid">Subtract ST(0) from ST(1), store result in ST(1), and pop register stack.</td>
</tr>
<tr>
<td class="grid"><code>DA /4</code></td>
<td class="grid"><code>FISUB m32int</code></td>
<td class="grid">Subtract m32int from ST(0) and store result in ST(0).</td>
</tr>
<tr>
<td class="grid"><code>DE /4</code></td>
<td class="grid"><code>FISUB m16int</code></td>
<td class="grid">Subtract m16int from ST(0) and store result in ST(0).</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Subtracts the source operand from the destination operand and stores the difference in the destination location. The destination operand is always an FPU data register; the source operand can be a register or a memory location. Source operands in memory can be in single-precision or double-precision floating-point format or in word or doubleword integer format.</p>
<p>The no-operand version of the instruction subtracts the contents of the ST(0) register from the ST(1) register and stores the result in ST(1). The one-operand version subtracts the contents of a memory location (either a floating-point or an integer value) from the contents of the ST(0) register and stores the result in ST(0). The two-operand version, subtracts the contents of the ST(0) register from the ST(i) register or vice versa.</p>
<p>The FSUBP instructions perform the additional operation of popping the FPU register stack following the subtraction. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1. The no-operand version of the floating-point subtract instructions always results in the register stack being popped. In some assemblers, the mnemonic for this instruction is FSUB rather than FSUBP.</p>
<p>The FISUB instructions convert an integer source operand to double extended-precision floating-point format before performing the subtraction.</p>
<p>The following table shows the results obtained when subtracting various classes of numbers from one another, assuming that neither overflow nor underflow occurs. Here, the Source value is subtracted from the Destination value (Destination - Source = result).</p>
<p>When the difference between two operands of like sign is 0, the result is +0, except for the round toward -infinite mode, in which case the result is -0. This instruction also guarantees that +0 - (-0) = +0, and that -0 - (+0) = -0. When the source operand is an integer 0, it is treated as a +0.</p>
<p>When one operand is infinite, the result is infinite of the expected sign. If both operands are infinite of the same sign, an invalid-operation exception is generated.</p>
<div>
<table class="grid">
<caption>FSUB/FSUBP/FISUB Results</caption>
<tr><td>- Source: -inf</td><td>Source: -F or -I</td><td>Source: -0</td><td>Source: +0</td><td>Source: +F or +I</td><td>Source: +inf</td><td>Source: NaN</td></tr>
<tr><td>Destination: -inf</td><td>*</td><td>-inf</td><td>-inf</td><td>-inf</td><td>-inf</td><td>-inf</td><td>NaN</td></tr>
<tr><td>Destination: -F</td><td>+inf</td><td>&Atilde;�&acirc;��&Atilde;�&Acirc;&plusmn;F</td><td>or</td><td>&Atilde;�&acirc;��&Atilde;�&Acirc;&plusmn;0</td><td>Destination</td><td>Destination</td><td>-F</td><td>-inf</td><td>NaN</td></tr>
<tr><td>Destination: -0</td><td>+inf</td><td>-Source</td><td>&Atilde;�&acirc;��&Atilde;�&Acirc;&plusmn;0</td><td>-0</td><td>-Source</td><td>-inf</td><td>NaN</td></tr>
<tr><td>Destination: +0</td><td>+inf</td><td>-Source</td><td>+0</td><td>&Atilde;�&acirc;��&Atilde;�&Acirc;&plusmn;0</td><td>-Source</td><td>-inf</td><td>NaN</td></tr>
<tr><td>Destination: +F</td><td>+inf</td><td>+F</td><td>Destination</td><td>Destination</td><td>&Atilde;�&acirc;��&Atilde;�&Acirc;&plusmn;F</td><td>or</td><td>&Atilde;�&acirc;��&Atilde;�&Acirc;&plusmn;0</td><td>-inf</td><td>NaN</td></tr>
<tr><td>Destination: +inf</td><td>+inf</td><td>+inf</td><td>+inf</td><td>+inf</td><td>+8</td><td>*</td><td>NaN</td></tr>
<tr><td>Destination: NaN</td><td>NaN</td><td>NaN</td><td>NaN</td><td>NaN</td><td>NaN</td><td>NaN</td><td>NaN</td></tr>
<tfoot>
<tr><td colspan="8">F Means finite floating-point value.</td></tr>
<tr><td colspan="8">I Means integer.</td></tr>
<tr><td colspan="8">* Indicates floating-point invalid-arithmetic-operand (#IA) exception.</td></tr>
</tfoot>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre><span class="keyword">if</span><span class="operator">(</span>Instruction <span class="operator">==</span> FISUB<span class="operator">)</span> Destination <span class="operator">=</span> Destination <span class="operator">-</span> ConvertToExtendedDouble<span class="operator">(</span>Source<span class="operator">)</span><span class="operator">;</span>
<span class="keyword">else</span> Destination <span class="operator">=</span> Destination <span class="operator">-</span> Source<span class="operator">;</span> <span class="comment">//source operand is floating-point value</span>

<span class="keyword">if</span><span class="operator">(</span>Instruction <span class="operator">==</span> FSUBP<span class="operator">)</span> PopRegisterStack<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>FPU flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>C1 Set to 0 if stack underflow occurred.
Set if result was rounded up; cleared otherwise.
C0, C2, C3 Undefined.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Floating-Point Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#IS</code></td><td>Stack underflow occurred.</td></tr>
<tr><td><code>#IS</code></td><td>Stack underflow occurred.</td></tr>
<tr><td><code>#IA</code></td><td>Operand is an SNaN value or unsupported format. Operands are infinities of like sign.</td></tr>
<tr><td><code>#D</code></td><td>Source operand is a denormal value.</td></tr>
<tr><td><code>#U</code></td><td>Result is too small for destination format.</td></tr>
<tr><td><code>#O</code></td><td>Result is too large for destination format.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#GP</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#SS</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Instruction</th>
<th>Latency</th>
<th>Throughput</th>
<th>Execution Unit</th>
</tr>
<tr><td class="grid"><code>CPUID</code></td><td class="grid">0F3n/0F2n</td><td class="grid">0F3n/0F2n</td><td class="grid">0F2n</td></tr>
<tr><td class="grid"><code>FSUB</code></td><td class="grid">6/5</td><td class="grid">1/1</td><td class="grid">FP_ADD</td></tr>
</table>
</object>
</div>
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>FSUBR/FSUBRP/FISUBR: Reverse Subtract (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>FSUBR/FSUBRP/FISUBR: Reverse Subtract (x86 Instruction Set Reference)</title>
<h1>FSUBR/FSUBRP/FISUBR</h1>
<h2>Reverse Subtract</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>D8 /5</code></td>
<td class="grid"><code>FSUBR m32fp</code></td>
<td class="grid">Subtract ST(0) from m32fp and store result in ST(0).</td>
</tr>
<tr>
<td class="grid"><code>DC /5</code></td>
<td class="grid"><code>FSUBR m64fp</code></td>
<td class="grid">Subtract ST(0) from m64fp and store result in ST(0).</td>
</tr>
<tr>
<td class="grid"><code>D8 E8+i</code></td>
<td class="grid"><code>FSUBR ST(0), ST(i)</code></td>
<td class="grid">Subtract ST(0) from ST(i) and store result in ST(0).</td>
</tr>
<tr>
<td class="grid"><code>DC E0+i</code></td>
<td class="grid"><code>FSUBR ST(i), ST(0)</code></td>
<td class="grid">Subtract ST(i) from ST(0) and store result in ST(i).</td>
</tr>
<tr>
<td class="grid"><code>DE E0+i</code></td>
<td class="grid"><code>FSUBRP ST(i), ST(0)</code></td>
<td class="grid">Subtract ST(i) from ST(0), store result in ST(i), and pop register stack.</td>
</tr>
<tr>
<td class="grid"><code>DE E1</code></td>
<td class="grid"><code>FSUBRP</code></td>
<td class="grid">Subtract ST(1) from ST(0), store result in ST(1), and pop register stack.</td>
</tr>
<tr>
<td class="grid"><code>DA /5</code></td>
<td class="grid"><code>FISUBR m32int</code></td>
<td class="grid">Subtract ST(0) from m32int and store result in ST(0).</td>
</tr>
<tr>
<td class="grid"><code>DE /5</code></td>
<td class="grid"><code>FISUBR m16int</code></td>
<td class="grid">Subtract ST(0) from m16int and store result in ST(0).</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Subtracts the destination operand from the source operand and stores the difference in the destination location. The destination operand is always an FPU register; the source operand can be a register or a memory location. Source operands in memory can be in single-precision or doubleprecision floating-point format or in word or doubleword integer format.</p>
<p>These instructions perform the reverse operations of the FSUB, FSUBP, and FISUB instructions.</p>
<p>They are provided to support more efficient coding.</p>
<p>The no-operand version of the instruction subtracts the contents of the ST(1) register from the ST(0) register and stores the result in ST(1). The one-operand version subtracts the contents of the ST(0) register from the contents of a memory location (either a floating-point or an integer value) and stores the result in ST(0). The two-operand version, subtracts the contents of the ST(i) register from the ST(0) register or vice versa.</p>
<p>The FSUBRP instructions perform the additional operation of popping the FPU register stack following the subtraction. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1. The no-operand version of the floating-point reverse subtract instructions always results in the register stack being popped. In some assemblers, the mnemonic for this instruction is FSUBR rather than FSUBRP.</p>
<p>The FISUBR instructions convert an integer source operand to double extended-precision floating-point format before performing the subtraction.</p>
<p>The following table shows the results obtained when subtracting various classes of numbers from one another, assuming that neither overflow nor underflow occurs. Here, the Destination value is subtracted from the Source value (Source - Destination = result).</p>
<p>When the difference between two operands of like sign is 0, the result is +0, except for the round toward -infinite mode, in which case the result is -0. This instruction also guarantees that +0 - (-0) = +0, and that -0 - (+0) = -0. When the source operand is an integer 0, it is treated as a +0.</p>
<p>When one operand is infinite, the result is infinite of the expected sign. If both operands are infinite of the same sign, an invalid-operation exception is generated.</p>
<div>
<table class="grid">
<caption>FSUBR/FSUBRP/FISUBR Results</caption>
<tr><td>- Source: -inf</td><td>Source: -F or -I</td><td>Source: -0</td><td>Source: +0</td><td>Source: +F or +I</td><td>Source: +inf</td><td>Source: NaN</td></tr>
<tr><td>Destination: -inf</td><td>*</td><td>-inf</td><td>-inf</td><td>-inf</td><td>-inf</td><td>-inf</td><td>NaN</td></tr>
<tr><td>Destination: -F</td><td>+inf</td><td>&Atilde;�&acirc;��&Atilde;�&Acirc;&plusmn;F</td><td>or</td><td>&Atilde;�&acirc;��&Atilde;�&Acirc;&plusmn;0</td><td>Destination</td><td>Destination</td><td>-F</td><td>-inf</td><td>NaN</td></tr>
<tr><td>Destination: -0</td><td>+inf</td><td>-Source</td><td>&Atilde;�&acirc;��&Atilde;�&Acirc;&plusmn;0</td><td>-0</td><td>-Source</td><td>-inf</td><td>NaN</td></tr>
<tr><td>Destination: +0</td><td>+inf</td><td>-Source</td><td>+0</td><td>&Atilde;�&acirc;��&Atilde;�&Acirc;&plusmn;0</td><td>-Source</td><td>-inf</td><td>NaN</td></tr>
<tr><td>Destination: +F</td><td>+inf</td><td>+F</td><td>Destination</td><td>Destination</td><td>&Atilde;�&acirc;��&Atilde;�&Acirc;&plusmn;F</td><td>or</td><td>&Atilde;�&acirc;��&Atilde;�&Acirc;&plusmn;0</td><td>-inf</td><td>NaN</td></tr>
<tr><td>Destination: +inf</td><td>+inf</td><td>+inf</td><td>+inf</td><td>+inf</td><td>+8</td><td>*</td><td>NaN</td></tr>
<tr><td>Destination: NaN</td><td>NaN</td><td>NaN</td><td>NaN</td><td>NaN</td><td>NaN</td><td>NaN</td><td>NaN</td></tr>
<tfoot>
<tr><td colspan="8">F Means finite floating-point value.</td></tr>
<tr><td colspan="8">I Means integer.</td></tr>
<tr><td colspan="8">* Indicates floating-point invalid-arithmetic-operand (#IA) exception.</td></tr>
</tfoot>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre><span class="keyword">if</span><span class="operator">(</span>Instruction <span class="operator">=</span> FISUBR<span class="operator">)</span> Destination <span class="operator">=</span> ConvertToExtendedDouble<span class="operator">(</span>Source<span class="operator">)</span> <span class="operator">-</span> Destination<span class="operator">;</span>
<span class="keyword">else</span> Destination <span class="operator">=</span> Source <span class="operator">-</span> Destination<span class="operator">;</span> <span class="comment">//source operand is floating-point value</span>

<span class="keyword">if</span><span class="operator">(</span>Instruction <span class="operator">==</span> FSUBRP<span class="operator">)</span> PopRegisterStack<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>FPU flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>C1 Set to 0 if stack underflow occurred.
Set if result was rounded up; cleared otherwise.
C0, C2, C3 Undefined.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Floating-Point Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#IS</code></td><td>Stack underflow occurred.</td></tr>
<tr><td><code>#IS</code></td><td>Stack underflow occurred.</td></tr>
<tr><td><code>#IA</code></td><td>Operand is an SNaN value or unsupported format. Operands are infinities of like sign.</td></tr>
<tr><td><code>#D</code></td><td>Source operand is a denormal value.</td></tr>
<tr><td><code>#U</code></td><td>Result is too small for destination format.</td></tr>
<tr><td><code>#O</code></td><td>Result is too large for destination format.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#GP</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#SS</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
</div>
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>FTST: Test Floating Point Value (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>FTST: Test Floating Point Value (x86 Instruction Set Reference)</title>
<h1>FTST</h1>
<h2>Test Floating Point Value</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>D9 E4</code></td>
<td class="grid"><code>FTST</code></td>
<td class="grid">Compare ST(0) with 0.0.</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Compares the value in the ST(0) register with 0.0 and sets the condition code flags C0, C2, and C3 in the FPU status word according to the results (see table below).</p>
<div>
<table class="grid">
<caption>FTST Results</caption>
<tr><th>Condition</th><th>C3</th><th>C2</th><th>C0</th></tr>
<tr><td>ST(0) &gt; 0.0</td><td>0</td><td>0</td><td>0</td></tr>
<tr><td>ST(0) &lt; 0.0</td><td>0</td><td>0</td><td>1</td></tr>
<tr><td>ST(0) = 0.0</td><td>1</td><td>0</td><td>0</td></tr>
<tr><td>Unordered</td><td>1</td><td>1</td><td>1</td></tr>
</table>
</div>
<p>This instruction performs an &quot;unordered comparison.&quot; An unordered comparison also checks the class of the numbers being compared (see &quot;FXAM-Examine&quot; in this chapter). If the value in register ST(0) is a NaN or is in an undefined format, the condition flags are set to &quot;unordered&quot; and the invalid operation exception is generated.</p>
<p>The sign of zero is ignored, so that -0.0 = +0.0.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre>OperandRelation <span class="operator">=</span> Compare<span class="operator">(</span>ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">,</span> <span class="number">0.0</span><span class="operator">)</span><span class="operator">;</span>
<span class="keyword">switch</span><span class="operator">(</span>OperandRelation<span class="operator">)</span> {
	RelationGreaterThan<span class="operator">:</span>
		C3 <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
		C2 <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
		C0 <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
		<span class="keyword">break</span><span class="operator">;</span>
	RelationLessThan<span class="operator">:</span>
		C3 <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
		C2 <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
		C0 <span class="operator">=</span> <span class="number">1</span><span class="operator">;</span>
		<span class="keyword">break</span><span class="operator">;</span>
	RelationEqual<span class="operator">:</span>
		C3 <span class="operator">=</span> <span class="number">1</span><span class="operator">;</span>
		C2 <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
		C0 <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
		<span class="keyword">break</span><span class="operator">;</span>
	RelationUnordered
		C3 <span class="operator">=</span> <span class="number">1</span><span class="operator">;</span>
		C2 <span class="operator">=</span> <span class="number">1</span><span class="operator">;</span>
		C0 <span class="operator">=</span> <span class="number">1</span><span class="operator">;</span>
		<span class="keyword">break</span><span class="operator">;</span>
}
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>FPU flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>C1 Set to 0 if stack underflow occurred; otherwise, set to 0.
C0, C2, C3 See table above.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Floating-Point Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#IS</code></td><td>Stack underflow occurred.</td></tr>
<tr><td><code>#IS</code></td><td>Stack underflow occurred.</td></tr>
<tr><td><code>#IA</code></td><td>The source operand is a NaN value or is in an unsupported format.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
</div>
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>FUCOM/FUCOMP/FUCOMPP: Unordered Compare Floating Point Values (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>FUCOM/FUCOMP/FUCOMPP: Unordered Compare Floating Point Values (x86 Instruction Set Reference)</title>
<h1>FUCOM/FUCOMP/FUCOMPP</h1>
<h2>Unordered Compare Floating Point Values</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>DD E0+i</code></td>
<td class="grid"><code>FUCOM ST(i)</code></td>
<td class="grid">Compare ST(0) with ST(i).</td>
</tr>
<tr>
<td class="grid"><code>DD E1</code></td>
<td class="grid"><code>FUCOM</code></td>
<td class="grid">Compare ST(0) with ST(1).</td>
</tr>
<tr>
<td class="grid"><code>DD E8+i</code></td>
<td class="grid"><code>FUCOMP ST(i)</code></td>
<td class="grid">Compare ST(0) with ST(i) and pop register stack.</td>
</tr>
<tr>
<td class="grid"><code>DD E9</code></td>
<td class="grid"><code>FUCOMP</code></td>
<td class="grid">Compare ST(0) with ST(1) and pop register stack.</td>
</tr>
<tr>
<td class="grid"><code>DA E9</code></td>
<td class="grid"><code>FUCOMPP</code></td>
<td class="grid">Compare ST(0) with ST(1) and pop register stack twice.</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Performs an unordered comparison of the contents of register ST(0) and ST(i) and sets condition code flags C0, C2, and C3 in the FPU status word according to the results (see the table below).</p>
<p>If no operand is specified, the contents of registers ST(0) and ST(1) are compared. The sign of zero is ignored, so that -0.0 is equal to +0.0.</p>
<div>
<table class="grid">
<caption>FUCOM/FUCOMP/FUCOMPP Results</caption>
<tr><th>Comparison Results</th><th>C3</th><th>C2</th><th>C0</th></tr>
<tr><td>ST(0) &gt; ST(i)</td><td>0</td><td>0</td><td>0</td></tr>
<tr><td>ST(0) &lt; ST(i)</td><td>0</td><td>0</td><td>1</td></tr>
<tr><td>ST(0) = ST(i)</td><td>1</td><td>0</td><td>0</td></tr>
<tr><td>Unordered</td><td>1</td><td>1</td><td>1</td></tr>
<tfoot>
<tr><td colspan="4">* Flags not set if unmasked invalid-arithmetic-operand (#IA) exception is generated.</td></tr>
</tfoot>
</table>
</div>
<p>An unordered comparison checks the class of the numbers being compared (see &quot;FXAM-Examine&quot; in this chapter). The FUCOM/FUCOMP/FUCOMPP instructions perform the same operations as the FCOM/FCOMP/FCOMPP instructions. The only difference is that the FUCOM/FUCOMP/FUCOMPP instructions raise the invalid-arithmetic-operand exception (#IA) only when either or both operands are an SNaN or are in an unsupported format; QNaNs cause the condition code flags to be set to unordered, but do not cause an exception to be generated.</p>
<p>The FCOM/FCOMP/FCOMPP instructions raise an invalid-operation exception when either or both of the operands are a NaN value of any kind or are in an unsupported format.</p>
<p>As with the FCOM/FCOMP/FCOMPP instructions, if the operation results in an invalid-arithmetic- operand exception being raised, the condition code flags are set only if the exception is masked.</p>
<p>The FUCOMP instruction pops the register stack following the comparison operation and the FUCOMPP instruction pops the register stack twice following the comparison operation. To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre>OperandRelation <span class="operator">=</span> Compare<span class="operator">(</span>ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">,</span> Source<span class="operator">)</span><span class="operator">;</span>
<span class="keyword">switch</span><span class="operator">(</span>OperandRelation<span class="operator">)</span> {
	RelationGreaterThan<span class="operator">:</span>
		C3 <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
		C2 <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
		C0 <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
		<span class="keyword">break</span><span class="operator">;</span>
	RelationLessThan<span class="operator">:</span>
		C3 <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
		C2 <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
		C0 <span class="operator">=</span> <span class="number">1</span><span class="operator">;</span>
		<span class="keyword">break</span><span class="operator">;</span>
	RelationEqual<span class="operator">:</span>
		C3 <span class="operator">=</span> <span class="number">1</span><span class="operator">;</span>
		C2 <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
		C0 <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
		<span class="keyword">break</span><span class="operator">;</span>
}

<span class="keyword">if</span><span class="operator">(</span>IsQNaN<span class="operator">(</span>ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span> <span class="operator">||</span> IsQNaN<span class="operator">(</span>Source<span class="operator">)</span><span class="operator">)</span> {
	C3 <span class="operator">=</span> <span class="number">1</span><span class="operator">;</span>
	C2 <span class="operator">=</span> <span class="number">1</span><span class="operator">;</span>
	C0 <span class="operator">=</span> <span class="number">1</span><span class="operator">;</span>
}
<span class="keyword">else</span> {
	Exception<span class="operator">(</span>IA<span class="operator">)</span><span class="operator">;</span>
	<span class="keyword">if</span><span class="operator">(</span>FPUControlWord<span class="operator">.</span>IM <span class="operator">==</span> <span class="number">1</span><span class="operator">)</span> {
		C3 <span class="operator">=</span> <span class="number">1</span><span class="operator">;</span>
		C2 <span class="operator">=</span> <span class="number">1</span><span class="operator">;</span>
		C0 <span class="operator">=</span> <span class="number">1</span><span class="operator">;</span>
	}
}

<span class="keyword">if</span><span class="operator">(</span>Instruction <span class="operator">==</span> FUCOMP<span class="operator">)</span> PopRegisterStack<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span>
<span class="keyword">if</span><span class="operator">(</span>Instruction <span class="operator">==</span> FUCOMPP<span class="operator">)</span> {
	PopRegisterStack<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span>
	PopRegisterStack<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span>
}
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>FPU flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>C1 Set to 0 if stack underflow occurred.
C0, C2, C3 See table above.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Floating-Point Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#IS</code></td><td>Stack underflow occurred.</td></tr>
<tr><td><code>#IS</code></td><td>Stack underflow occurred.</td></tr>
<tr><td><code>#IA</code></td><td>One or both operands are SNaN values or have unsupported formats. Detection of a QNaN value in and of itself does not raise an invalidoperand exception.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
</div>
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>FXAM: Examine Floating Point Value (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>FXAM: Examine Floating Point Value (x86 Instruction Set Reference)</title>
<h1>FXAM</h1>
<h2>Examine Floating Point Value</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>D9 E5</code></td>
<td class="grid"><code>FXAM</code></td>
<td class="grid">Classify value or number in ST(0).</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Examines the contents of the ST(0) register and sets the condition code flags C0, C2, and C3 in the FPU status word to indicate the class of value or number in the register (see the table below).</p>
<div>
<table class="grid">
<caption>FXAM Results</caption>
<tr><th>Class</th><th>C3</th><th>C2</th><th>C0</th></tr>
<tr><td>Unsupported</td><td>0</td><td>0</td><td>0</td></tr>
<tr><td>NaN</td><td>0</td><td>0</td><td>1</td></tr>
<tr><td>Normal finite number</td><td>0</td><td>1</td><td>0</td></tr>
<tr><td>Infinity</td><td>0</td><td>1</td><td>1</td></tr>
<tr><td>Zero</td><td>1</td><td>0</td><td>0</td></tr>
<tr><td>Empty</td><td>1</td><td>0</td><td>1</td></tr>
<tr><td>Denormal number</td><td>1</td><td>1</td><td>0</td></tr>
</table>
</div>
<p>The C1 flag is set to the sign of the value in ST(0), regardless of whether the register is empty or full.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre>C1 <span class="operator">=</span> GetSignBit<span class="operator">(</span>ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
<span class="keyword">switch</span><span class="operator">(</span>GetClass<span class="operator">(</span>ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span><span class="operator">)</span> {
	<span class="keyword">case</span> ClassUnsupported<span class="operator">:</span>
		C3 <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
		C2 <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
		C0 <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
		<span class="keyword">break</span><span class="operator">;</span>
	<span class="keyword">case</span> ClassNormal<span class="operator">:</span>
		C3 <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
		C2 <span class="operator">=</span> <span class="number">1</span><span class="operator">;</span>
		C0 <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
		<span class="keyword">break</span><span class="operator">;</span>
	<span class="keyword">case</span> ClassInfinity<span class="operator">:</span>
		C3 <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
		C2 <span class="operator">=</span> <span class="number">1</span><span class="operator">;</span>
		C0 <span class="operator">=</span> <span class="number">1</span><span class="operator">;</span>
		<span class="keyword">break</span><span class="operator">;</span>
	<span class="keyword">case</span> ClassZero<span class="operator">:</span>
		C3 <span class="operator">=</span> <span class="number">1</span><span class="operator">;</span>
		C2 <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
		C0 <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
		<span class="keyword">break</span><span class="operator">;</span>
	<span class="keyword">case</span> ClassEmpty<span class="operator">:</span>
		C3 <span class="operator">=</span> <span class="number">1</span><span class="operator">;</span>
		C2 <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
		C0 <span class="operator">=</span> <span class="number">1</span><span class="operator">;</span>
		<span class="keyword">break</span><span class="operator">;</span>
	<span class="keyword">case</span> ClassDenormal<span class="operator">:</span>
		C3 <span class="operator">=</span> <span class="number">1</span><span class="operator">;</span>
		C2 <span class="operator">=</span> <span class="number">1</span><span class="operator">;</span>
		C0 <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
		<span class="keyword">break</span><span class="operator">;</span>
}
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>FPU flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>C1 Sign of value in ST(0).
C0, C2, C3 See table above.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Floating-Point Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
None.
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
</div>
</body>
</html>

Added doc/x86/html/file_module_x86_id_126.html.





































































































































































































































































































































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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>FXCH: Exchange Register Contents (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>FXCH: Exchange Register Contents (x86 Instruction Set Reference)</title>
<h1>FXCH</h1>
<h2>Exchange Register Contents</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>D9 C8+i</code></td>
<td class="grid"><code>FXCH ST(i)</code></td>
<td class="grid">Exchange the contents of ST(0) and ST(i).</td>
</tr>
<tr>
<td class="grid"><code>D9 C9</code></td>
<td class="grid"><code>FXCH</code></td>
<td class="grid">Exchange the contents of ST(0) and ST(1).</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Exchanges the contents of registers ST(0) and ST(i). If no source operand is specified, the contents of ST(0) and ST(1) are exchanged.</p>
<p>This instruction provides a simple means of moving values in the FPU register stack to the top of the stack [ST(0)], so that they can be operated on by those floating-point instructions that can only operate on values in ST(0). For example, the following instruction sequence takes the square root of the third register from the top of the register stack:</p>
<p>FXCH ST(3);</p>
<p>FSQRT;</p>
<p>FXCH ST(3);</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre><span class="keyword">if</span><span class="operator">(</span>NumberOfOperands <span class="operator">==</span> <span class="number">1</span><span class="operator">)</span> {
	Temporary <span class="operator">=</span> ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">;</span>
	ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span> <span class="operator">=</span> Source<span class="operator">;</span>
	Source <span class="operator">=</span> Temporary<span class="operator">;</span>
}
<span class="keyword">else</span> {
	Temporary <span class="operator">=</span> ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">;</span>
	ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span> <span class="operator">=</span> ST<span class="operator">(</span><span class="number">1</span><span class="operator">)</span><span class="operator">;</span>
	ST<span class="operator">(</span><span class="number">1</span><span class="operator">)</span> <span class="operator">=</span> Temporary<span class="operator">;</span>
}
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>FPU flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>C1 Set to 0 if stack underflow occurred; otherwise, set to 0.
C0, C2, C3 Undefined.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Floating-Point Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#IS</code></td><td>Stack underflow occurred.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Instruction</th>
<th>Latency</th>
<th>Throughput</th>
<th>Execution Unit</th>
</tr>
<tr><td class="grid"><code>CPUID</code></td><td class="grid">0F3n/0F2n</td><td class="grid">0F3n/0F2n</td><td class="grid">0F2n</td></tr>
<tr><td class="grid"><code>FXCH</code></td><td class="grid">0</td><td class="grid">1</td><td class="grid">FP_MOVE</td></tr>
</table>
</object>
</div>
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>FXRSTOR: Restore x87 FPU, MMX Technology, SSE, and SSE2 State (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>FXRSTOR: Restore x87 FPU, MMX Technology, SSE, and SSE2 State (x86 Instruction Set Reference)</title>
<h1>FXRSTOR</h1>
<h2>Restore x87 FPU, MMX Technology, SSE, and SSE2 State</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>0F AE /1</code></td>
<td class="grid"><code>FXRSTOR m512byte Restore the x87 FPU, MMX technology, XMM, and MXCSR register state from m512byte.</code></td>
<td class="grid"></td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Reloads the x87 FPU, MMX technology, XMM, and MXCSR registers from the 512-byte memory image specified in the source operand. This data should have been written to memory previously using the FXSAVE instruction, and the first byte of the data should be located on a 16-byte boundary. The FXSAVE table shows the layout of the state information in memory and describes the fields in the memory image for the FXRSTOR and FXSAVE instructions.</p>
<p>The state image referenced with an FXRSTOR instruction must have been saved using an FXSAVE instruction or be in the same format as that shown in Table 3-47. Referencing a state image saved with an FSAVE or FNSAVE instruction will result in an incorrect state restoration.</p>
<p>The FXRSTOR instruction does not flush pending x87 FPU exceptions. To check and raise exceptions when loading x87 FPU state information with the FXRSTOR instruction, use an FWAIT instruction after the FXRSTOR instruction.</p>
<p>If the OSFXSR bit in control register CR4 is not set, the FXRSTOR instruction may not restore the states of the XMM and MXCSR registers. This behavior is implementation dependent.</p>
<p>If the MXCSR state contains an unmasked exception with a corresponding status flag also set, loading the register with the FXRSTOR instruction will not result in an SIMD floating-point error condition being generated. Only the next occurrence of this unmasked exception will result in the exception being generated.</p>
<p>Bit 6 and bits 16 through 32 of the MXCSR register are defined as reserved and should be set to 0. Attempting to write a 1 in any of these bits from the saved state image will result in a general protection exception (#GP) being generated.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre><span class="operator">(</span>x87 FPU<span class="operator">,</span> MMX<span class="operator">,</span> XMM7<span class="operator">-</span>XMM0<span class="operator">,</span> MXCSR<span class="operator">)</span> <span class="operator">=</span> Load<span class="operator">(</span>Source<span class="operator">)</span><span class="operator">;</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Floating-Point Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
None.
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>SIMD Floating-Point Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
None.
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. (See alignment check exception [#AC] below.)</td></tr>
<tr><td><code>#GP(0)</code></td><td>For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment. (See alignment check exception [#AC] below.)</td></tr>
<tr><td><code>#SS(0)</code></td><td>For an illegal address in the SS segment.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>For a page fault.</td></tr>
<tr><td><code>#NM</code></td><td>If TS in CR0 is set.</td></tr>
<tr><td><code>#UD</code></td><td>If EM in CR0 is set. If CPUID feature flag FXSR is 0. If instruction is preceded by a LOCK prefix.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH.</td></tr>
<tr><td><code>#NM</code></td><td>If TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
Same exceptions as in Real Address Mode
<div>
<table class="operations_table">
<tr><td><code>#PF(fault-code)</code></td><td>For a page fault.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>For a page fault.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Instruction</th>
<th>Latency</th>
<th>Throughput</th>
<th>Execution Unit</th>
</tr>
<tr><td class="grid"><code>CPUID</code></td><td class="grid">0F3n/0F2n/069n</td><td class="grid">0F3n/0F2n/069n</td><td class="grid">0F2n</td></tr>
<tr><td class="grid"><code>FXRSTOR</code></td><td class="grid">150</td><td class="grid">-</td><td class="grid">-</td></tr>
</table>
</object>
</div>
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>FXSAVE: Save x87 FPU, MMX Technology, SSE, and SSE2 State (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>FXSAVE: Save x87 FPU, MMX Technology, SSE, and SSE2 State (x86 Instruction Set Reference)</title>
<h1>FXSAVE</h1>
<h2>Save x87 FPU, MMX Technology, SSE, and SSE2 State</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>0F AE /0</code></td>
<td class="grid"><code>FXSAVE m512byte</code></td>
<td class="grid">Save the x87 FPU, MMX technology, XMM, and MXCSR register state to m512byte.</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Saves the current state of the x87 FPU, MMX technology, XMM, and MXCSR registers to a 512-byte memory location specified in the destination operand. The following table shows the layout of the state information in memory.</p>
<div>
<table class="grid">
<caption>Layout of FXSAVE and FXRSTOR Memory Region</caption>
<tr><th>Bit #</th><th>Description</th></tr>
<tr><td>0-1</td><td>FCW</td></tr>
<tr><td>2-3</td><td>FSW</td></tr>
<tr><td>4</td><td>FTW</td></tr>
<tr><td>5</td><td>Reserved</td></tr>
<tr><td>6-7</td><td>FOP</td></tr>
<tr><td>8-11</td><td>FPU IP</td></tr>
<tr><td>12-13</td><td>CS</td></tr>
<tr><td>14-15</td><td>Reserved</td></tr>
<tr><td>16-19</td><td>FPU DP</td></tr>
<tr><td>20-21</td><td>DS</td></tr>
<tr><td>22-23</td><td>Reserved</td></tr>
<tr><td>24-27</td><td>MXCSR</td></tr>
<tr><td>28-31</td><td>MXCSR_MASK</td></tr>
<tr><td>32-41</td><td>ST0/MM0</td></tr>
<tr><td>42-47</td><td>Reserved</td></tr>
<tr><td>48-57</td><td>ST1/MM1</td></tr>
<tr><td>58-63</td><td>Reserved</td></tr>
<tr><td>64-73</td><td>ST2/MM2</td></tr>
<tr><td>74-79</td><td>Reserved</td></tr>
<tr><td>80-89</td><td>ST3/MM3</td></tr>
<tr><td>90-95</td><td>Reserved</td></tr>
<tr><td>96-105</td><td>ST4/MM4</td></tr>
<tr><td>106-111</td><td>Reserved</td></tr>
<tr><td>112-121</td><td>ST5/MM5</td></tr>
<tr><td>122-127</td><td>Reserved</td></tr>
<tr><td>128-137</td><td>ST6/MM6</td></tr>
<tr><td>138-143</td><td>Reserved</td></tr>
<tr><td>144-153</td><td>ST7/MM7</td></tr>
<tr><td>154-159</td><td>Reserved</td></tr>
<tr><td>160-175</td><td>XMM0</td></tr>
<tr><td>176-191</td><td>XMM1</td></tr>
<tr><td>192-207</td><td>XMM2</td></tr>
<tr><td>208-223</td><td>XMM3</td></tr>
<tr><td>224-239</td><td>XMM4</td></tr>
<tr><td>240-255</td><td>XMM5</td></tr>
<tr><td>256-271</td><td>XMM6</td></tr>
<tr><td>272-287</td><td>XMM7</td></tr>
<tr><td>288-512</td><td>Reserved</td></tr>
</table>
</div>
<p>The destination operand contains the first byte of the memory image, and it must be aligned on a 16-byte boundary. A misaligned destination operand will result in a general-protection (#GP) exception being generated (or in some cases, an alignment check exception [#AC]).</p>
<p>The FXSAVE instruction is used when an operating system needs to perform a context switch or when an exception handler needs to save and examine the current state of the x87 FPU, MMX technology, and/or XMM and MXCSR registers.</p>
<p>The fields in the table above are as follows:</p>
<dl>
<dt>FCW</dt>
<dd>x87 FPU Control Word (16 bits). See Figure 8-6 in the IA-32 Intel Architecture Software Developer's Manual, Volume 1, for the layout of the x87 FPU control word.</dd>
<dt>FSW</dt>
<dd>x87 FPU Status Word (16 bits). See Figure 8-4 in the IA-32 Intel Architecture Software Developer's Manual, Volume 1, for the layout of the x87 FPU status word.</dd>
<dt>FTW</dt>
<dd>x87 FPU Tag Word (8 bits). The tag information saved here is abridged, as described in the following paragraphs. See Figure 8-7 in the IA-32 Intel Architecture Software Developer's Manual, Volume 1, for the layout of the x87 FPU tag word.</dd>
<dt>FOP</dt>
<dd>x87 FPU Opcode (16 bits). The lower 11 bits of this field contain the opcode, upper 5 bits are reserved. See Figure 8-8 in the IA-32 Intel Architecture Software Developer's Manual, Volume 1, for the layout of the x87 FPU opcode field.</dd>
<dt>FPU</dt>
<dd>IP x87 FPU Instruction Pointer Offset (32 bits). The contents of this field differ depending on the current addressing mode (32-bit or 16-bit) of the processor when the FXSAVE instruction was executed: 32-bit mode -&gt; 32-bit IP offset, 16-bit mode -&gt; low 16 bits are IP offset with the high 16 bits being reserved. See &quot;x87 FPU Instruction and Operand (Data) Pointers&quot; in Chapter 8 of the IA-32 Intel Architecture Software Developer's Manual, Volume 1, for a description of the x87 FPU instruction pointer.</dd>
<dt>CS</dt>
<dd>x87 FPU Instruction Pointer Selector (16 bits).</dd>
<dt>FPU</dt>
<dd>DP x87 FPU Instruction Operand (Data) Pointer Offset (32 bits). The contents of this field differ depending on the current addressing mode (32-bit or 16- bit) of the processor when the FXSAVE instruction was executed: 32-bit mode -&gt; 32-bit IP offset, 16-bit mode -&gt; low 16 bits are IP offset with the high 16 bits being reserved. See &quot;x87 FPU Instruction and Operand (Data) Pointers&quot; in Chapter 8 of the IA-32 Intel Architecture Software Developer's Manual, Volume 1, for a description of the x87 FPU operand pointer.</dd>
<dt>DS</dt>
<dd>x87 FPU Instruction Operand (Data) Pointer Selector (16 bits).</dd>
<dt>MXCSR</dt>
<dd>MXCSR Register State (32 bits). See Figure 10-3 in the IA-32 Intel Architecture Software Developer's Manual, Volume 1, for the layout of the MXCSR register. If the OSFXSR bit in control register CR4 is not set, the FXSAVE instruction may not save this register. This behavior is implementation dependent.</dd>
<dt>MXCSR_MASK</dt>
<dd>MXCSR_MASK (32 bits). This mask can be used to adjust values written to the MXCSR register, ensuring that reserved bits are set to 0. Set the mask bits and flags in MXCSR to the mode of operation desired for SSE and SSE2 SIMD floating-point instructions. See &quot;Guidelines for Writing to the MXCSR Register&quot; in Chapter 11 of the IA-32 Intel Architecture Software Developer's Manual, Volume 1, for instructions for how to determine and use the MXCSR_MASK value.</dd>
<dt>ST0/MM0 through ST7/MM7</dt>
<dd>x87 FPU or MMX technology registers. These 80-bit fields contain the x87 FPU data registers or the MMX technology registers, depending on the state of the processor prior to the execution of the FXSAVE instruction. If the processor had been executing x87 FPU instruction prior to the FXSAVE instruction, the x87 FPU data registers are saved; if it had been executing MMX instructions (or SSE or SSE2 instructions that operated on the MMX technology registers), the MMX technology registers are saved. When the MMX technology registers are saved, the high 16 bits of the field are reserved.</dd>
<dt>XMM0 through XMM7</dt>
<dd>XMM registers (128 bits per field). If the OSFXSR bit in control register CR4 is not set, the FXSAVE instruction may not save these registers. This behavior is implementation dependent.</dd>
</dl>
<p>The FXSAVE instruction saves an abridged version of the x87 FPU tag word in the FTW field (unlike the FSAVE instruction, which saves the complete tag word). The tag information is saved in physical register order (R0 through R7), rather than in top-of-stack (TOS) order. With the FXSAVE instruction, however, only a single bit (1 for valid or 0 for empty) is saved for each tag. For example, assume that the tag word is currently set as follows:</p>
<div>
<table class="grid">
<tr><th>R7</th><th>R6</th><th>R5</th><th>R4</th><th>R3</th><th>R2</th><th>R1</th><th>R0</th></tr>
<tr><td>[body]11</td><td>xx</td><td>xx</td><td>xx</td><td>11</td><td>11</td><td>11</td><td>11[/body]</td></tr>
<tfoot>
<tr><td colspan="8">Here, 11B indicates empty stack elements and &quot;xx&quot; indicates valid (00B), zero (01B), or special (10B).</td></tr>
</tfoot>
</table>
</div>
<p>For this example, the FXSAVE instruction saves only the following 8 bits of information:</p>
<div>
<table class="grid">
<tr><th>R7</th><th>R6</th><th>R5</th><th>R4</th><th>R3</th><th>R2</th><th>R1</th><th>R0</th></tr>
<tr><td>[body]0</td><td>1</td><td>1</td><td>1</td><td>0</td><td>0</td><td>0</td><td>0[/body]</td></tr>
<tfoot>
<tr><td colspan="8">Here, a 1 is saved for any valid, zero, or special tag, and a 0 is saved for any empty tag.</td></tr>
</tfoot>
</table>
</div>
<p>The operation of the FXSAVE instruction differs from that of the FSAVE instruction, the as follows:</p>
<ul>
<li>FXSAVE instruction does not check for pending unmasked floating-point exceptions. (The FXSAVE operation in this regard is similar to the operation of the FNSAVE instruction).</li>
<li>After the FXSAVE instruction has saved the state of the x87 FPU, MMX technology, XMM, and MXCSR registers, the processor retains the contents of the registers. Because of this behavior, the FXSAVE instruction cannot be used by an application program to pass a &quot;clean&quot; x87 FPU state to a procedure, since it retains the current state. To clean the x87 FPU state, an application must explicitly execute an FINIT instruction after an FXSAVE instruction to reinitialize the x87 FPU state.</li>
<li>The format of the memory image saved with the FXSAVE instruction is the same regardless of the current addressing mode (32-bit or 16-bit) and operating mode (protected, real address, or system management). This behavior differs from the FSAVE instructions, where the memory image format is different depending on the addressing mode and operating mode. Because of the different image formats, the memory image saved with the FXSAVE instruction cannot be restored correctly with the FRSTOR instruction, and likewise the state saved with the FSAVE instruction cannot be restored correctly with the FXRSTOR instruction.</li>
</ul>
<p>Note that The FSAVE format for FTW can be recreated from the FTW valid bits and the stored 80-bit FP data (assuming the stored data was not the contents of MMX technology registers) using the following table:</p>
<div>
<table class="grid">
<caption>Recreating FSAVE Format</caption>
<tr><th>Exponent all 1's</th><th>Exponent all 0's</th><th>Fraction all 0's</th><th>J and M bits</th><th>FTW valid bit</th><th>x87 FTW</th></tr>
<tr><td>0</td><td>0</td><td>0</td><td>0x</td><td>1</td><td>Special 10</td></tr>
<tr><td>0</td><td>0</td><td>0</td><td>1x</td><td>1</td><td>Valid 00</td></tr>
<tr><td>0</td><td>0</td><td>1</td><td>00</td><td>1</td><td>Special 10</td></tr>
<tr><td>0</td><td>0</td><td>1</td><td>10</td><td>1</td><td>Valid 00</td></tr>
<tr><td>0</td><td>1</td><td>0</td><td>0x</td><td>1</td><td>Special 10</td></tr>
<tr><td>0</td><td>1</td><td>0</td><td>1x</td><td>1</td><td>Special 10</td></tr>
<tr><td>0</td><td>1</td><td>1</td><td>00</td><td>1</td><td>Zero 01</td></tr>
<tr><td>0</td><td>1</td><td>1</td><td>10</td><td>1</td><td>Special 10</td></tr>
<tr><td>1</td><td>0</td><td>0</td><td>1x</td><td>1</td><td>Special 10</td></tr>
<tr><td>1</td><td>0</td><td>0</td><td>1x</td><td>1</td><td>Special 10</td></tr>
<tr><td>1</td><td>0</td><td>1</td><td>00</td><td>1</td><td>Special 10</td></tr>
<tr><td>1</td><td>0</td><td>1</td><td>10</td><td>1</td><td>Special 10</td></tr>
<tr><td>Any legal</td><td>Any legal</td><td>Any legal</td><td>Any legal</td><td>0</td><td>Empty 11</td></tr>
</table>
</div>
<p>The J-bit is defined to be the 1-bit binary integer to the left of the decimal place in the mantissa.</p>
<p>The M-bit is defined to be the most significant bit of the fractional portion of the mantissa (i.e., the bit immediately to the right of the decimal place).</p>
<p>When the M-bit is the most significant bit of the fractional portion of the mantissa, it must be 0 if the fraction is all 0's.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre>Destination <span class="operator">=</span> Save<span class="operator">(</span>x87 FPU<span class="operator">,</span> MMX<span class="operator">,</span> XMM7<span class="operator">-</span>XMM0<span class="operator">,</span> MXCSR<span class="operator">)</span><span class="operator">;</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH.</td></tr>
<tr><td><code>#NM</code></td><td>If TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Instruction</th>
<th>Latency</th>
<th>Throughput</th>
<th>Execution Unit</th>
</tr>
<tr><td class="grid"><code>CPUID</code></td><td class="grid">0F3n/0F2n/069n</td><td class="grid">0F3n/0F2n/069n</td><td class="grid">0F2n</td></tr>
<tr><td class="grid"><code>FXSAVE</code></td><td class="grid">100</td><td class="grid">-</td><td class="grid">-</td></tr>
</table>
</object>
</div>
</body>
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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>FXTRACT: Extract Exponent and Mantissa (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>FXTRACT: Extract Exponent and Mantissa (x86 Instruction Set Reference)</title>
<h1>FXTRACT</h1>
<h2>Extract Exponent and Mantissa</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>D9 F4</code></td>
<td class="grid"><code>FXTRACT</code></td>
<td class="grid">Separate value in ST(0) into exponent and mantissa, store exponent in ST(0), and push the mantissa onto the register stack.</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Separates the source value in the ST(0) register into its exponent and mantissa, stores the exponent in ST(0), and pushes the mantissa onto the register stack. Following this operation, the new top-of-stack register ST(0) contains the value of the original mantissa expressed as a floating-point value. The sign and mantissa of this value are the same as those found in the source operand, and the exponent is 3FFFH (biased value for a true exponent of zero). The ST(1) register contains the value of the original operand's true (unbiased) exponent expressed as a floating-point value. (The operation performed by this instruction is a superset of the IEEErecommended logb(x) function.) This instruction and the F2XM1 instruction are useful for performing power and range scaling operations. The FXTRACT instruction is also useful for converting numbers in double extended-precision floating-point format to decimal representations (e.g., for printing or displaying).</p>
<p>If the floating-point zero-divide exception (#Z) is masked and the source operand is zero, an exponent value of -infinite is stored in register ST(1) and 0 with the sign of the source operand is stored in register ST(0).</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre>Temporary <span class="operator">=</span> GetMantissa<span class="operator">(</span>ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span> <span class="operator">=</span> GetExponent<span class="operator">(</span>ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
Top <span class="operator">=</span> Top <span class="operator">-</span> <span class="number">1</span><span class="operator">;</span>
ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span> <span class="operator">=</span> Temporary<span class="operator">;</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>FPU flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>C1 Set to 0 if stack underflow occurred; set to 1 if stack overflow occurred.
C0, C2, C3 Undefined.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Floating-Point Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#IS</code></td><td>Stack underflow or overflow occurred.</td></tr>
<tr><td><code>#IS</code></td><td>Stack underflow or overflow occurred.</td></tr>
<tr><td><code>#IA</code></td><td>Source operand is an SNaN value or unsupported format.</td></tr>
<tr><td><code>#Z</code></td><td>ST(0) operand is +-0.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
</div>
</body>
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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>ANDPD: Bitwise Logical AND of Packed Double-Precision Floating-Point Values (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>ANDPD: Bitwise Logical AND of Packed Double-Precision Floating-Point Values (x86 Instruction Set Reference)</title>
<h1>ANDPD</h1>
<h2>Bitwise Logical AND of Packed Double-Precision Floating-Point Values</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>66 0F 54 /r</code></td>
<td class="grid"><code>ANDPD xmm1, xmm2/m128</code></td>
<td class="grid">Bitwise logical AND of xmm2/m128 and xmm1. If any part of the operand lies outside the effective address space from 0 to FFFFH.</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Performs a bitwise logical AND of the two packed double-precision floating-point values from the source operand (second operand) and the destination operand (first operand), and stores the result in the destination operand. The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre>Destination<span class="operator">[</span><span class="number">0..127</span><span class="operator">]</span> <span class="operator">=</span> Destination<span class="operator">[</span><span class="number">0..127</span><span class="operator">]</span> <span class="operator">&amp;</span> Source<span class="operator">[</span><span class="number">0..127</span><span class="operator">]</span><span class="operator">;</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>SIMD Floating-Point Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
None.
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#GP(0)</code></td><td>For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#SS(0)</code></td><td>For an illegal address in the SS segment.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>For a page fault.</td></tr>
<tr><td><code>#NM</code></td><td>If TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
Same exceptions as in Real Address Mode
<div>
<table class="operations_table">
<tr><td><code>#PF(fault-code)</code></td><td>For a page fault.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>For a page fault.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>For a page fault.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
</div>
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>FYL2X: Compute y * log_2(x) (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>FYL2X: Compute y * log_2(x) (x86 Instruction Set Reference)</title>
<h1>FYL2X</h1>
<h2>Compute y * log_2(x)</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>D9 F1</code></td>
<td class="grid"><code>FYL2X</code></td>
<td class="grid">Replace ST(1) with (ST(1) * log_2(ST(0))) and pop the register stack.</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Computes (ST(1) * log_2 (ST(0))), stores the result in resister ST(1), and pops the FPU register stack. The source operand in ST(0) must be a non-zero positive number.</p>
<p>The following table shows the results obtained when taking the log of various classes of numbers, assuming that neither overflow nor underflow occurs.</p>
<div>
<table class="grid">
<caption>FYL2X Results</caption>
<tr><td>-</td><td>ST(0): -inf</td><td>ST(0): -F</td><td>ST(0): +-0</td><td>ST(0): +0 &lt;</td><td>+F &lt; +1</td><td>+1</td><td>ST(0): +F &gt; +1</td><td>+inf</td><td>NaN</td></tr>
<tr><td>ST(1): -inf</td><td>*</td><td>*</td><td>+inf</td><td>+inf</td><td>*</td><td>-inf</td><td>-inf</td><td>NaN</td></tr>
<tr><td>ST(1): -F</td><td>*</td><td>*</td><td>**</td><td>+F</td><td>-0</td><td>-F</td><td>-inf</td><td>NaN</td></tr>
<tr><td>ST(1): -0</td><td>*</td><td>*</td><td>*</td><td>+0</td><td>-0</td><td>-0</td><td>*</td><td>NaN</td></tr>
<tr><td>ST(1): +0</td><td>*</td><td>*</td><td>*</td><td>-0</td><td>+0</td><td>+0</td><td>*</td><td>NaN</td></tr>
<tr><td>ST(1): +F</td><td>*</td><td>*</td><td>**</td><td>-F</td><td>+0</td><td>+F</td><td>+inf</td><td>NaN</td></tr>
<tr><td>ST(1): +inf</td><td>*</td><td>*</td><td>-inf</td><td>-inf</td><td>*</td><td>+inf</td><td>+inf</td><td>NaN</td></tr>
<tr><td>ST(1): NaN</td><td>NaN</td><td>NaN</td><td>NaN</td><td>NaN</td><td>NaN</td><td>NaN</td><td>NaN</td><td>NaN</td></tr>
<tfoot>
<tr><td colspan="9">F Means finite floating-point value.</td></tr>
<tr><td colspan="9">* Indicates floating-point invalid-operation (#IA) exception.</td></tr>
<tr><td colspan="9">** Indicates floating-point zero-divide (#Z) exception.</td></tr>
</tfoot>
<tr><td>If the divide-by-zero exception is masked and register ST(0) contains +-0, the instruction returns infinite with a sign that is the opposite of the sign of the source operand in register ST(1).</td></tr>
<tr><td>The FYL2X instruction is designed with a built-in multiplication to optimize the calculation of logarithms with an arbitrary positive base (b):</td></tr>
<tr><td>[code]</td></tr>
<tr><td>log_b(x) = log_2(x) / log_2(b)</td></tr>
<tr><td>[/code]</td></tr>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre>ST<span class="operator">(</span><span class="number">1</span><span class="operator">)</span> <span class="operator">=</span> ST<span class="operator">(</span><span class="number">1</span><span class="operator">)</span> <span class="operator">*</span> log_2<span class="operator">(</span>ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
PopRegisterStack<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>FPU flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>C1 Set to 0 if stack underflow occurred.
Set if result was rounded up; cleared otherwise.
C0, C2, C3 Undefined.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Floating-Point Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#IS</code></td><td>Stack underflow occurred.</td></tr>
<tr><td><code>#IS</code></td><td>Stack underflow occurred.</td></tr>
<tr><td><code>#IA</code></td><td>Either operand is an SNaN or unsupported format. Source operand in register ST(0) is a negative finite value (not -0).</td></tr>
<tr><td><code>#Z</code></td><td>Source operand in register ST(0) is +-0.</td></tr>
<tr><td><code>#D</code></td><td>Source operand is a denormal value.</td></tr>
<tr><td><code>#U</code></td><td>Result is too small for destination format.</td></tr>
<tr><td><code>#O</code></td><td>Result is too large for destination format.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Instruction</th>
<th>Latency</th>
<th>Throughput</th>
<th>Execution Unit</th>
</tr>
<tr><td class="grid"><code>CPUID</code></td><td class="grid">0F3n/0F2n</td><td class="grid">0F3n/0F2n</td><td class="grid">0F2n</td></tr>
<tr><td class="grid"><code>FYL2X</code></td><td class="grid">100-250/140-190</td><td class="grid">85</td><td class="grid">-</td></tr>
</table>
</object>
</div>
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>FYL2XP1: Compute y * log_2(x + 1) (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>FYL2XP1: Compute y * log_2(x + 1) (x86 Instruction Set Reference)</title>
<h1>FYL2XP1</h1>
<h2>Compute y * log_2(x + 1)</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>D9 F9</code></td>
<td class="grid"><code>FYL2XP1</code></td>
<td class="grid">Replace ST(1) with ST(1) * log_2(ST(0) + 1.0) and pop the register stack.</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Computes (ST(1) * log_2(ST(0) + 1.0)), stores the result in register ST(1), and pops the FPU register stack. The source operand in ST(0) must be in the range:</p>
<pre>sqrt(2) / 2 - 1 to 1 + sqrt(2) / 2
</pre>
<p>The source operand in ST(1) can range from -infinite to +infinite. If the ST(0) operand is outside of its acceptable range, the result is undefined and software should not rely on an exception being generated. Under some circumstances exceptions may be generated when ST(0) is out of range, but this behavior is implementation specific and not guaranteed.</p>
<p>The following table shows the results obtained when taking the log epsilon of various classes of numbers, assuming that underflow does not occur.</p>
<div>
<table class="grid">
<caption>FYL2XP1 Results</caption>
<tr><td>-</td><td>ST(0): -(1 - sqrt(2) / 2) to -0</td><td>-0</td><td>ST(0): +0</td><td>ST(0): +0 to +(1 - sqrt(2) / 2)</td><td>ST(0): Nan</td></tr>
<tr><td>ST(1): -inf</td><td>+inf</td><td>*</td><td>*</td><td>-inf</td><td>NaN</td></tr>
<tr><td>ST(1): -F</td><td>+F</td><td>+0</td><td>-0</td><td>-F</td><td>NaN</td></tr>
<tr><td>ST(1): -0</td><td>+0</td><td>+0</td><td>-0</td><td>-0</td><td>NaN</td></tr>
<tr><td>ST(1): +0</td><td>-0</td><td>-0</td><td>+0</td><td>+0</td><td>NaN</td></tr>
<tr><td>ST(1): +F</td><td>-F</td><td>-0</td><td>+0</td><td>+F</td><td>NaN</td></tr>
<tr><td>ST(1): +inf</td><td>-inf</td><td>*</td><td>*</td><td>+inf</td><td>NaN</td></tr>
<tr><td>ST(1): NaN</td><td>NaN</td><td>NaN</td><td>NaN</td><td>NaN</td><td>NaN</td></tr>
<tfoot>
<tr><td colspan="6">F Means finite floating-point value.</td></tr>
<tr><td colspan="6">* Indicates floating-point invalid-operation (#IA) exception.</td></tr>
</tfoot>
</table>
</div>
<p>This instruction provides optimal accuracy for values of epsilon [the value in register ST(0)] that are close to 0. For small epsilon (?) values, more significant digits can be retained by using the FYL2XP1 instruction than by using (?+1) as an argument to the FYL2X instruction. The (?+1) expression is commonly found in compound interest and annuity calculations. The result can be simply converted into a value in another logarithm base by including a scale factor in the ST(1) source operand. The following equation is used to calculate the scale factor for a particular logarithm base, where n is the logarithm base desired for the result of the FYL2XP1 instruction:</p>
<pre>scale factor = log_n(2)

</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre>ST<span class="operator">(</span><span class="number">1</span><span class="operator">)</span> <span class="operator">=</span> ST<span class="operator">(</span><span class="number">1</span><span class="operator">)</span> <span class="operator">*</span> log_2<span class="operator">(</span>ST<span class="operator">(</span><span class="number">0</span><span class="operator">)</span> <span class="operator">+</span> <span class="number">1.0</span><span class="operator">)</span><span class="operator">;</span>
PopRegisterStack<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span>
<span class="operator">[</span>/code<span class="operator">]</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>FPU flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>C1 Set to 0 if stack underflow occurred.
Set if result was rounded up; cleared otherwise.
C0, C2, C3 Undefined.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Floating-Point Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#IS</code></td><td>Stack underflow occurred.</td></tr>
<tr><td><code>#IS</code></td><td>Stack underflow occurred.</td></tr>
<tr><td><code>#IA</code></td><td>Either operand is an SNaN value or unsupported format.</td></tr>
<tr><td><code>#D</code></td><td>Source operand is a denormal value.</td></tr>
<tr><td><code>#U</code></td><td>Result is too small for destination format.</td></tr>
<tr><td><code>#O</code></td><td>Result is too large for destination format.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#NM</code></td><td>EM or TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Instruction</th>
<th>Latency</th>
<th>Throughput</th>
<th>Execution Unit</th>
</tr>
<tr><td class="grid"><code>CPUID</code></td><td class="grid">0F3n/0F2n</td><td class="grid">0F3n/0F2n</td><td class="grid">0F2n</td></tr>
<tr><td class="grid"><code>FYL2XP1 140-190</code></td><td class="grid">85</td><td class="grid">-</td></tr>
</table>
</object>
</div>
</body>
</html>

Added doc/x86/html/file_module_x86_id_132.html.

















































































































































































































































































































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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>HADDPD: Packed Double-FP Horizontal Add (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>HADDPD: Packed Double-FP Horizontal Add (x86 Instruction Set Reference)</title>
<h1>HADDPD</h1>
<h2>Packed Double-FP Horizontal Add</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>66 0F 7C /r</code></td>
<td class="grid"><code>HADDPD xmm1, xmm2/m128</code></td>
<td class="grid">Add horizontally packed DP FP numbers from xmm2/m128 to xmm1.</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Adds the double-precision floating-point values in the high and low quadwords of the destination operand and stores the result in the low quadword of the destination operand.</p>
<p>Adds the double-precision floating-point values in the high and low quadwords of the source operand and stores the result in the high quadword of the destination operand.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre>xmm1<span class="operator">[</span><span class="number">0..63</span><span class="operator">]</span> <span class="operator">=</span> xmm1<span class="operator">[</span><span class="number">0..63</span><span class="operator">]</span> <span class="operator">+</span> xmm1<span class="operator">[</span><span class="number">64..127</span><span class="operator">]</span><span class="operator">;</span>
xmm1<span class="operator">[</span><span class="number">64..127</span><span class="operator">]</span> <span class="operator">=</span> xmm2/m128<span class="operator">[</span><span class="number">0..63</span><span class="operator">]</span> <span class="operator">+</span> xmm2/m128<span class="operator">[</span><span class="number">64..127</span><span class="operator">]</span><span class="operator">;</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
When the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated.
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Numeric Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
Overflow, Underflow, Invalid, Precision, Denormal.
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#GP(0)</code></td><td>For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#SS(0)</code></td><td>For an illegal address in the SS segment.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>For a page fault.</td></tr>
<tr><td><code>#NM</code></td><td>If TS bit in CR0 is set.</td></tr>
<tr><td><code>#XM</code></td><td>For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT = 1).</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#NM</code></td><td>If TS bit in CR0 is set.</td></tr>
<tr><td><code>#XM</code></td><td>For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT = 1).</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#NM</code></td><td>If TS bit in CR0 is set.</td></tr>
<tr><td><code>#XM</code></td><td>For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT = 1).</td></tr>
<tr><td><code>#UD</code></td><td>If CR0.EM = 1. For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT = 0). If CR4.OSFXSR(bit 9) = 0. If CPUID.SSE3(ECX bit 0) = 0.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Instruction</th>
<th>Latency</th>
<th>Throughput</th>
<th>Execution Unit</th>
</tr>
<tr><td class="grid"><code>CPUID</code></td><td class="grid">0F3n</td><td class="grid">0F3n</td><td class="grid">0F3n</td></tr>
<tr><td class="grid"><code>HADDPD</code></td><td class="grid">13</td><td class="grid">4</td><td class="grid">FP_ADD FP_MISC</td></tr>
</table>
</object>
</div>
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>HADDPS: Packed Single-FP Horizontal Add (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>HADDPS: Packed Single-FP Horizontal Add (x86 Instruction Set Reference)</title>
<h1>HADDPS</h1>
<h2>Packed Single-FP Horizontal Add</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>F2 0F 7C /r</code></td>
<td class="grid"><code>HADDPS xmm1, xmm2/m128</code></td>
<td class="grid">Add horizontally packed SP FP numbers from xmm2/m128 to xmm1.</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Adds the single-precision floating-point values in the first and second dwords of the destination operand and stores the result in the first dword of the destination operand.</p>
<p>Adds single-precision floating-point values in the third and fourth dword of the destination operand and stores the result in the second dword of the destination operand.</p>
<p>Adds single-precision floating-point values in the first and second dword of the source operand and stores the result in the third dword of the destination operand.</p>
<p>Adds single-precision floating-point values in the third and fourth dword of the source operand and stores the result in the fourth dword of the destination operand.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre>xmm1<span class="operator">[</span><span class="number">0..31</span><span class="operator">]</span> <span class="operator">=</span> xmm1<span class="operator">[</span><span class="number">0..31</span><span class="operator">]</span> <span class="operator">+</span> xmm1<span class="operator">[</span><span class="number">32..63</span><span class="operator">]</span><span class="operator">;</span>
xmm1<span class="operator">[</span><span class="number">32..63</span><span class="operator">]</span> <span class="operator">=</span> xmm1<span class="operator">[</span><span class="number">64..95</span><span class="operator">]</span> <span class="operator">+</span> xmm1<span class="operator">[</span><span class="number">96..127</span><span class="operator">]</span><span class="operator">;</span>
xmm1<span class="operator">[</span><span class="number">64..95</span><span class="operator">]</span> <span class="operator">=</span> xmm2/m128<span class="operator">[</span><span class="number">0..31</span><span class="operator">]</span> <span class="operator">+</span> xmm2/m128<span class="operator">[</span><span class="number">32..63</span><span class="operator">]</span><span class="operator">;</span>
xmm1<span class="operator">[</span><span class="number">96..127</span><span class="operator">]</span> <span class="operator">=</span> xmm2/m128<span class="operator">[</span><span class="number">64..95</span><span class="operator">]</span> <span class="operator">+</span> xmm2/m128<span class="operator">[</span><span class="number">96..127</span><span class="operator">]</span><span class="operator">;</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
When the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated.
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Numeric Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
Overflow, Underflow, Invalid, Precision, Denormal.
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#GP(0)</code></td><td>For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#SS(0)</code></td><td>For an illegal address in the SS segment.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>For a page fault.</td></tr>
<tr><td><code>#NM</code></td><td>If TS bit in CR0 is set.</td></tr>
<tr><td><code>#XM</code></td><td>For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT = 1).</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#NM</code></td><td>If TS bit in CR0 is set.</td></tr>
<tr><td><code>#XM</code></td><td>For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT = 1).</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#NM</code></td><td>If TS bit in CR0 is set.</td></tr>
<tr><td><code>#XM</code></td><td>For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT = 1).</td></tr>
<tr><td><code>#UD</code></td><td>If CR0.EM = 1. For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT = 0). If CR4.OSFXSR(bit 9) = 0. If CPUID.SSE3(ECX bit 0) = 0.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Instruction</th>
<th>Latency</th>
<th>Throughput</th>
<th>Execution Unit</th>
</tr>
<tr><td class="grid"><code>CPUID</code></td><td class="grid">0F3n</td><td class="grid">0F3n</td><td class="grid">0F3n</td></tr>
<tr><td class="grid"><code>HADDPS</code></td><td class="grid">13</td><td class="grid">4</td><td class="grid">FP_ADD FP_MISC</td></tr>
</table>
</object>
</div>
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>HLT: Halt (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>HLT: Halt (x86 Instruction Set Reference)</title>
<h1>HLT</h1>
<h2>Halt</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>F4</code></td>
<td class="grid"><code>HLT</code></td>
<td class="grid">Halt.</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Stops instruction execution and places the processor in a HALT state. An enabled interrupt (including NMI and SMI), a debug exception, the BINIT# signal, the INIT# signal, or the RESET# signal will resume execution. If an interrupt (including NMI) is used to resume execution after a HLT instruction, the saved instruction pointer (CS:EIP) points to the instruction following the HLT instruction.</p>
<p>When a HLT instruction is executed on an IA-32 processor supporting Hyper-Threading Technology, only the logical processor that executes the instruction is halted. The other logical processors in the physical processor remain active, unless they are each individually halted by executing a HLT instruction.</p>
<p>The HLT instruction is a privileged instruction. When the processor is running in protected or virtual-8086 mode, the privilege level of a program or procedure must be 0 to execute the HLT instruction.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre>EnterHaltstate<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>None.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If the current privilege level is not 0.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
None.
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If the current privilege level is not 0.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
</div>
</body>
</html>

Added doc/x86/html/file_module_x86_id_135.html.



















































































































































































































































































































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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>HSUBPD: Packed Double-FP Horizontal Subtract (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>HSUBPD: Packed Double-FP Horizontal Subtract (x86 Instruction Set Reference)</title>
<h1>HSUBPD</h1>
<h2>Packed Double-FP Horizontal Subtract</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>66 0F 7D /r</code></td>
<td class="grid"><code>HSUBPD xmm1, xmm2/m128</code></td>
<td class="grid">Subtract horizontally packed DP FP numbers in xmm2/m128 from xmm1.</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>The HSUBPD instruction subtracts horizontally the packed DP FP numbers of both operands.</p>
<p>Subtracts the double-precision floating-point value in the high quadword of the destination operand from the low quadword of the destination operand and stores the result in the low quadword of the destination operand.</p>
<p>Subtracts the double-precision floating-point value in the high quadword of the source operand from the low quadword of the source operand and stores the result in the high quadword of the destination operand.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre>xmm1<span class="operator">[</span><span class="number">0..63</span><span class="operator">]</span> <span class="operator">=</span> xmm1<span class="operator">[</span><span class="number">0..63</span><span class="operator">]</span> <span class="operator">-</span> xmm1<span class="operator">[</span><span class="number">64..127</span><span class="operator">]</span><span class="operator">;</span>
xmm1<span class="operator">[</span><span class="number">64..127</span><span class="operator">]</span> <span class="operator">=</span> xmm2/m128<span class="operator">[</span><span class="number">0..63</span><span class="operator">]</span> <span class="operator">-</span> xmm2/m128<span class="operator">[</span><span class="number">64..127</span><span class="operator">]</span><span class="operator">;</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
When the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated.
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Numeric Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
Overflow, Underflow, Invalid, Precision, Denormal.
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#GP(0)</code></td><td>For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#SS(0)</code></td><td>For an illegal address in the SS segment.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>For a page fault.</td></tr>
<tr><td><code>#NM</code></td><td>If TS bit in CR0 is set.</td></tr>
<tr><td><code>#XM</code></td><td>For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT = 1).</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#NM</code></td><td>If TS bit in CR0 is set.</td></tr>
<tr><td><code>#XM</code></td><td>For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT = 1).</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#NM</code></td><td>If TS bit in CR0 is set.</td></tr>
<tr><td><code>#XM</code></td><td>For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT = 1).</td></tr>
<tr><td><code>#UD</code></td><td>If CR0.EM = 1. For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT = 0). If CR4.OSFXSR(bit 9) = 0. If CPUID.SSE3(ECX bit 0) = 0.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Instruction</th>
<th>Latency</th>
<th>Throughput</th>
<th>Execution Unit</th>
</tr>
<tr><td class="grid"><code>CPUID</code></td><td class="grid">0F3n</td><td class="grid">0F3n</td><td class="grid">0F3n</td></tr>
<tr><td class="grid"><code>HSUBPD</code></td><td class="grid">13</td><td class="grid">4</td><td class="grid">FP_ADD FP_MISC</td></tr>
</table>
</object>
</div>
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>HSUBPS: Packed Single-FP Horizontal Subtract (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>HSUBPS: Packed Single-FP Horizontal Subtract (x86 Instruction Set Reference)</title>
<h1>HSUBPS</h1>
<h2>Packed Single-FP Horizontal Subtract</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>F2 0F 7D /r</code></td>
<td class="grid"><code>HSUBPS xmm1, xmm2/m128</code></td>
<td class="grid">Subtract horizontally packed SP FP numbers in xmm2/m128 from xmm1.</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Subtracts the single-precision floating-point value in the second dword of the destination operand from the first dword of the destination operand and stores the result in the first dword of the destination operand.</p>
<p>Subtracts the single-precision floating-point value in the fourth dword of the destination operand from the third dword of the destination operand and stores the result in the second dword of the destination operand.</p>
<p>Subtracts the single-precision floating-point value in the second dword of the source operand from the first dword of the source operand and stores the result in the third dword of the destination operand.</p>
<p>Subtracts the single-precision floating-point value in the fourth dword of the source operand from the third dword of the source operand and stores the result in the fourth dword of the destination operand.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre>xmm1<span class="operator">[</span><span class="number">0..31</span><span class="operator">]</span> <span class="operator">=</span> xmm1<span class="operator">[</span><span class="number">0..31</span><span class="operator">]</span> <span class="operator">-</span> xmm1<span class="operator">[</span><span class="number">32..63</span><span class="operator">]</span><span class="operator">;</span>
xmm1<span class="operator">[</span><span class="number">32..63</span><span class="operator">]</span> <span class="operator">=</span> xmm1<span class="operator">[</span><span class="number">64..95</span><span class="operator">]</span> <span class="operator">-</span> xmm1<span class="operator">[</span><span class="number">96..127</span><span class="operator">]</span><span class="operator">;</span>
xmm1<span class="operator">[</span><span class="number">64..95</span><span class="operator">]</span> <span class="operator">=</span> xmm2/m128<span class="operator">[</span><span class="number">0..31</span><span class="operator">]</span> <span class="operator">-</span> xmm2/m128<span class="operator">[</span><span class="number">32..63</span><span class="operator">]</span><span class="operator">;</span>
xmm1<span class="operator">[</span><span class="number">96..127</span><span class="operator">]</span> <span class="operator">=</span> xmm2/m128<span class="operator">[</span><span class="number">64..95</span><span class="operator">]</span> <span class="operator">-</span> xmm2/m128<span class="operator">[</span><span class="number">96..127</span><span class="operator">]</span><span class="operator">;</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
When the source operand is a memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated.
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Numeric Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
Overflow, Underflow, Invalid, Precision, Denormal.
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#GP(0)</code></td><td>For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#SS(0)</code></td><td>For an illegal address in the SS segment.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>For a page fault.</td></tr>
<tr><td><code>#NM</code></td><td>If TS bit in CR0 is set.</td></tr>
<tr><td><code>#XM</code></td><td>For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT = 1).</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#NM</code></td><td>If TS bit in CR0 is set.</td></tr>
<tr><td><code>#XM</code></td><td>For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT = 1).</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If any part of the operand would lie outside of the effective address space from 0 to 0FFFFH. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#NM</code></td><td>If TS bit in CR0 is set.</td></tr>
<tr><td><code>#XM</code></td><td>For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT = 1).</td></tr>
<tr><td><code>#UD</code></td><td>If CR0.EM = 1. For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT = 0). If CR4.OSFXSR(bit 9) = 0. If CPUID.SSE3(ECX bit 0) = 0.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Instruction</th>
<th>Latency</th>
<th>Throughput</th>
<th>Execution Unit</th>
</tr>
<tr><td class="grid"><code>CPUID</code></td><td class="grid">0F3n</td><td class="grid">0F3n</td><td class="grid">0F3n</td></tr>
<tr><td class="grid"><code>HSUBPS</code></td><td class="grid">13</td><td class="grid">4</td><td class="grid">FP_ADD FP_MISC</td></tr>
</table>
</object>
</div>
</body>
</html>

Added doc/x86/html/file_module_x86_id_137.html.













































































































































































































































































































































































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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>IDIV: Signed Divide (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>IDIV: Signed Divide (x86 Instruction Set Reference)</title>
<h1>IDIV</h1>
<h2>Signed Divide</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>F6 /7</code></td>
<td class="grid"><code>IDIV r/m8</code></td>
<td class="grid">Signed divide AX by r/m8, with result stored in AL = Quotient, AH = Remainder.</td>
</tr>
<tr>
<td class="grid"><code>F7 /7</code></td>
<td class="grid"><code>IDIV r/m16</code></td>
<td class="grid">Signed divide DX:AX by r/m16, with result stored in AX = Quotient, DX = Remainder.</td>
</tr>
<tr>
<td class="grid"><code>F7 /7</code></td>
<td class="grid"><code>IDIV r/m32</code></td>
<td class="grid">Signed divide EDX:EAX by r/m32, with result stored in EAX = Quotient, EDX = Remainder.</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Divides (signed) the value in the AX, DX:AX, or EDX:EAX registers (dividend) by the source operand (divisor) and stores the result in the AX (AH:AL), DX:AX, or EDX:EAX registers. The source operand can be a general-purpose register or a memory location. The action of this instruction depends on the operand size (dividend/divisor), as shown in the following table:</p>
<div>
<table class="grid">
<caption>IDIV Results</caption>
<tr><td>[header]Operand Size</td><td>Dividend</td><td>Divisor</td><td>Quotient</td><td>Remainder</td><td>Quotient Range[/header]</td></tr>
<tr><td>Word/byte</td><td>AX</td><td>r/m8</td><td>AL</td><td>AH</td><td>-2^8 to +2^8 - 1</td></tr>
<tr><td>Doubleword/word</td><td>DX:AX</td><td>r/m16</td><td>AX</td><td>DX</td><td>-2^16 to +2^16 - 1</td></tr>
<tr><td>Quadword/doubleword</td><td>EDX:EAX</td><td>r/m32</td><td>EAX</td><td>EDX</td><td>-2^31 to +2^32 - 1</td></tr>
</table>
</div>
<p>Non-integral results are truncated (chopped) towards 0. The sign of the remainder is always the same as the sign of the dividend. The absolute value of the remainder is always less than the absolute value of the divisor. Overflow is indicated with the #DE (divide error) exception rather than with the OF (overflow) flag.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre><span class="keyword">if</span><span class="operator">(</span>Source <span class="operator">==</span> <span class="number">0</span><span class="operator">)</span> Exception<span class="operator">(</span>DE<span class="operator">)</span><span class="operator">;</span> <span class="comment">//divide error</span>

<span class="keyword">if</span><span class="operator">(</span>OperandSize <span class="operator">==</span> <span class="number">8</span><span class="operator">)</span> { <span class="comment">//word/byte operation</span>
	Temporary <span class="operator">=</span> AX / Source<span class="operator">;</span> <span class="comment">//signed division</span>
	<span class="keyword">if</span><span class="operator">(</span>Temporary <span class="operator">&gt;</span> <span class="number">0x7F</span> <span class="operator">||</span> Temporary <span class="operator">&lt;</span> <span class="number">0x80</span><span class="operator">)</span> Exception<span class="operator">(</span>DE<span class="operator">)</span><span class="operator">;</span> <span class="comment">//f a positive result is greater than 7FH or a negative result is less than 80H</span>
	<span class="keyword">else</span> {
		AL <span class="operator">=</span> Temporary<span class="operator">;</span>
		AH <span class="operator">=</span> AX <span class="operator">%</span> Source<span class="operator">;</span> <span class="comment">//signed modulus</span>
	}
}
<span class="keyword">else</span> <span class="keyword">if</span><span class="operator">(</span>OperandSize <span class="operator">==</span> <span class="number">16</span><span class="operator">)</span> { <span class="comment">//doubleword/word operation</span>
	Temporary <span class="operator">=</span> DX<span class="operator">:</span>AX / Source<span class="operator">;</span> <span class="comment">//signed division</span>
	<span class="keyword">if</span><span class="operator">(</span>Temporary <span class="operator">&gt;</span> <span class="number">0x7FFF</span> <span class="operator">||</span> Temporary <span class="operator">&lt;</span> <span class="number">0x8000</span><span class="operator">)</span> Exception<span class="operator">(</span>DE<span class="operator">)</span><span class="operator">;</span> <span class="comment">//f a positive result is greater than 7FFFH or a negative result is less than 8000H</span>
	<span class="keyword">else</span> {
		AX <span class="operator">=</span> Temporary<span class="operator">;</span>
		DX <span class="operator">=</span> DX<span class="operator">:</span>AX <span class="operator">%</span> Source<span class="operator">;</span> <span class="comment">//signed modulus</span>
	}
}
<span class="keyword">else</span> { <span class="comment">//quadword/doubleword operation</span>
	Temporary <span class="operator">=</span> EDX<span class="operator">:</span>EAX / Source<span class="operator">;</span> <span class="comment">//signed division</span>
	<span class="keyword">if</span><span class="operator">(</span>Temporary <span class="operator">&gt;</span> <span class="number">0x7FFFFFFF</span> <span class="operator">||</span> Temporary <span class="operator">&lt;</span> <span class="number">0x80000000</span><span class="operator">)</span> Exception<span class="operator">(</span>DE<span class="operator">)</span><span class="operator">;</span> <span class="comment">//f a positive result is greater than 7FFFFFFFH or a negative result is less than 80000000H</span>
	<span class="keyword">else</span> {
		EAX <span class="operator">=</span> Temporary<span class="operator">;</span>
		EDX <span class="operator">=</span> EDX<span class="operator">:</span>EAX <span class="operator">%</span> Source<span class="operator">;</span> <span class="comment">//signed modulus</span>
	}
}
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>The CF, OF, SF, ZF, AF, and PF flags are undefined.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#DE</code></td><td>If the source operand (divisor) is 0. The signed result (quotient) is too large for the destination.</td></tr>
<tr><td><code>#DE</code></td><td>If the source operand (divisor) is 0. The signed result (quotient) is too large for the destination.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#DE</code></td><td>If the source operand (divisor) is 0. The signed result (quotient) is too large for the destination.</td></tr>
<tr><td><code>#DE</code></td><td>If the source operand (divisor) is 0. The signed result (quotient) is too large for the destination.</td></tr>
<tr><td><code>#GP</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#DE</code></td><td>If the source operand (divisor) is 0. The signed result (quotient) is too large for the destination.</td></tr>
<tr><td><code>#DE</code></td><td>If the source operand (divisor) is 0. The signed result (quotient) is too large for the destination.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Instruction</th>
<th>Latency</th>
<th>Throughput</th>
<th>Execution Unit</th>
</tr>
<tr><td class="grid"><code>CPUID</code></td><td class="grid">0F3n/0F2n</td><td class="grid">0F3n/0F2n</td><td class="grid">0F2n</td></tr>
<tr><td class="grid"><code>IDIV</code></td><td class="grid">66-80/56-70</td><td class="grid">30/23</td><td class="grid">-</td></tr>
</table>
</object>
</div>
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>IMUL: Signed Multiply (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>IMUL: Signed Multiply (x86 Instruction Set Reference)</title>
<h1>IMUL</h1>
<h2>Signed Multiply</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>F6 /5</code></td>
<td class="grid"><code>IMUL r/m8</code></td>
<td class="grid">AX = AL * r/m byte.</td>
</tr>
<tr>
<td class="grid"><code>F7 /5</code></td>
<td class="grid"><code>IMUL r/m16</code></td>
<td class="grid">DX:AX = AX * r/m word.</td>
</tr>
<tr>
<td class="grid"><code>F7 /5</code></td>
<td class="grid"><code>IMUL r/m32</code></td>
<td class="grid">EDX:EAX = EAX * r/m doubleword.</td>
</tr>
<tr>
<td class="grid"><code>0F AF /r</code></td>
<td class="grid"><code>IMUL r16,r/m16</code></td>
<td class="grid">word register = word register * r/m word.</td>
</tr>
<tr>
<td class="grid"><code>0F AF /r</code></td>
<td class="grid"><code>IMUL r32,r/m32</code></td>
<td class="grid">doubleword register = doubleword register * r/m doubleword.</td>
</tr>
<tr>
<td class="grid"><code>6B /r ib</code></td>
<td class="grid"><code>IMUL r16,r/m16,imm8</code></td>
<td class="grid">word register = r/m16 * sign-extended immediate byte.</td>
</tr>
<tr>
<td class="grid"><code>6B /r ib</code></td>
<td class="grid"><code>IMUL r32,r/m32,imm8</code></td>
<td class="grid">doubleword register = r/m32 * sign-extended immediate byte.</td>
</tr>
<tr>
<td class="grid"><code>6B /r ib</code></td>
<td class="grid"><code>IMUL r16,imm8</code></td>
<td class="grid">word register = word register * sign-extended immediate byte.</td>
</tr>
<tr>
<td class="grid"><code>6B /r ib</code></td>
<td class="grid"><code>IMUL r32,imm8</code></td>
<td class="grid">doubleword register = doubleword register * signextended immediate byte.</td>
</tr>
<tr>
<td class="grid"><code>69 /r iw</code></td>
<td class="grid"><code>IMUL r16,r/m16,imm16</code></td>
<td class="grid">word register = r/m16 * immediate word.</td>
</tr>
<tr>
<td class="grid"><code>69 /r id</code></td>
<td class="grid"><code>IMUL r32,r/m32,imm32</code></td>
<td class="grid">doubleword register = r/m32 * immediate doubleword.</td>
</tr>
<tr>
<td class="grid"><code>69 /r iw</code></td>
<td class="grid"><code>IMUL r16,imm16</code></td>
<td class="grid">word register = r/m16 * immediate word.</td>
</tr>
<tr>
<td class="grid"><code>69 /r id</code></td>
<td class="grid"><code>IMUL r32,imm32</code></td>
<td class="grid">doubleword register = r/m32 * immediate doubleword.</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Performs a signed multiplication of two operands. This instruction has three forms, depending on the number of operands.</p>
<p>- One-operand form. This form is identical to that used by the MUL instruction. Here, the source operand (in a general-purpose register or memory location) is multiplied by the value in the AL, AX, or EAX register (depending on the operand size) and the product is stored in the AX, DX:AX, or EDX:EAX registers, respectively.</p>
<p>- Two-operand form. With this form the destination operand (the first operand) is multiplied by the source operand (second operand). The destination operand is a generalpurpose register and the source operand is an immediate value, a general-purpose register, or a memory location. The product is then stored in the destination operand location.</p>
<p>- Three-operand form. This form requires a destination operand (the first operand) and two source operands (the second and the third operands). Here, the first source operand (which can be a general-purpose register or a memory location) is multiplied by the second source operand (an immediate value). The product is then stored in the destination operand (a general-purpose register).</p>
<p>When an immediate value is used as an operand, it is sign-extended to the length of the destination operand format.</p>
<p>The CF and OF flags are set when significant bit (including the sign bit) are carried into the upper half of the result. The CF and OF flags are cleared when the result (including the sign bit) fits exactly in the lower half of the result.</p>
<p>The three forms of the IMUL instruction are similar in that the length of the product is calculated to twice the length of the operands. With the one-operand form, the product is stored exactly in the destination. With the two- and three- operand forms, however, the result is truncated to the length of the destination before it is stored in the destination register. Because of this truncation, the CF or OF flag should be tested to ensure that no significant bits are lost.</p>
<p>The two- and three-operand forms may also be used with unsigned operands because the lower half of the product is the same regardless if the operands are signed or unsigned. The CF and OF flags, however, cannot be used to determine if the upper half of the result is non-zero.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre><span class="keyword">switch</span><span class="operator">(</span>NumberOfOperands<span class="operator">)</span> {
	<span class="keyword">case</span> <span class="number">1</span><span class="operator">:</span>
		<span class="keyword">if</span><span class="operator">(</span>OperandSize <span class="operator">==</span> <span class="number">8</span><span class="operator">)</span> {
			AX <span class="operator">=</span> AL <span class="operator">*</span> Source<span class="operator">;</span> <span class="comment">//signed multiplication</span>
			<span class="keyword">if</span><span class="operator">(</span>AL <span class="operator">==</span> AX<span class="operator">)</span> {
				CF <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
				OF <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
			}
			<span class="keyword">else</span> {
				CF <span class="operator">=</span> <span class="number">1</span><span class="operator">;</span>
				OF <span class="operator">=</span> <span class="number">1</span><span class="operator">;</span>
			}
		}
		<span class="keyword">else</span> <span class="keyword">if</span><span class="operator">(</span>OperandSize <span class="operator">==</span> <span class="number">16</span><span class="operator">)</span> {
			DX<span class="operator">:</span>AX <span class="operator">=</span> AX <span class="operator">*</span> Source<span class="operator">;</span> <span class="comment">//signed multiplication</span>
			<span class="keyword">if</span><span class="operator">(</span>SignExtendTo32<span class="operator">(</span>AX<span class="operator">)</span> <span class="operator">==</span> DX<span class="operator">:</span>AX<span class="operator">)</span> {
				CF <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
				OF <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
			}
			<span class="keyword">else</span> {
				CF <span class="operator">=</span> <span class="number">1</span><span class="operator">;</span>
				OF <span class="operator">=</span> <span class="number">1</span><span class="operator">;</span>
			}
		}
		<span class="keyword">else</span> { <span class="comment">//OperandSize == 32</span>
			EDX<span class="operator">:</span>EAX <span class="operator">=</span> EAX <span class="operator">*</span> Source<span class="operator">;</span> <span class="comment">//signed multiplication</span>
			<span class="keyword">if</span><span class="operator">(</span>EAX <span class="operator">==</span> EDX<span class="operator">:</span>EAX<span class="operator">)</span> {
				CF <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
				OF <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
			}
			<span class="keyword">else</span> {
				CF <span class="operator">=</span> <span class="number">1</span><span class="operator">;</span>
				OF <span class="operator">=</span> <span class="number">1</span><span class="operator">;</span>
			}
		}
		<span class="keyword">break</span><span class="operator">;</span>
	<span class="keyword">case</span> <span class="number">2</span><span class="operator">:</span>
		Temporary <span class="operator">=</span> Destination <span class="operator">*</span> Source<span class="operator">;</span> <span class="comment">//signed multiplication; Temporary is twice twice the Destination size</span>
		Destination <span class="operator">=</span> Destination <span class="operator">*</span> Source<span class="operator">;</span> <span class="comment">//signed multiplication</span>
		<span class="keyword">if</span><span class="operator">(</span>Temporary <span class="operator">==</span> Destination<span class="operator">)</span> {
			CF <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
			OF <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
		}
		<span class="keyword">else</span> {
			CF <span class="operator">=</span> <span class="number">1</span><span class="operator">;</span>
			OF <span class="operator">=</span> <span class="number">1</span><span class="operator">;</span>
		}
		<span class="keyword">break</span><span class="operator">;</span>
	<span class="keyword">case</span> <span class="number">3</span><span class="operator">:</span>
		Destination <span class="operator">=</span> Source1 <span class="operator">*</span> Source2<span class="operator">;</span> <span class="comment">//signed multiplication</span>
		Temporary <span class="operator">=</span> Source1 <span class="operator">*</span> Source2<span class="operator">;</span> <span class="comment">///signed multiplication; Temporary is twice twice the Source1 size</span>
		<span class="keyword">if</span><span class="operator">(</span>Temporary <span class="operator">==</span> Destination<span class="operator">)</span> {
			CF <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
			OF <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
		}
		<span class="keyword">else</span> {
			CF <span class="operator">=</span> <span class="number">1</span><span class="operator">;</span>
			OF <span class="operator">=</span> <span class="number">1</span><span class="operator">;</span>
		}
		<span class="keyword">break</span><span class="operator">;</span>
}
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>For the one operand form of the instruction, the CF and OF flags are set when significant bits are carried into the upper half of the result and cleared when the result fits exactly in the lower half of the result. For the two- and three-operand forms of the instruction, the CF and OF flags are set when the result must be truncated to fit in the destination operand size and cleared when the result fits exactly in the destination operand size. The SF, ZF, AF, and PF flags are undefined.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#GP</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Instruction</th>
<th>Latency</th>
<th>Throughput</th>
<th>Execution Unit</th>
</tr>
<tr><td class="grid"><code>CPUID</code></td><td class="grid">0F3n/0F2n/069n</td><td class="grid">0F3n/0F2n</td><td class="grid">0F2n</td></tr>
<tr><td class="grid"><code>IMUL r32</code></td><td class="grid">10/14/4</td><td class="grid">1/3</td><td class="grid">FP_MUL</td></tr>
<tr><td class="grid"><code>IMUL imm32</code></td><td class="grid">-/14/4</td><td class="grid">1/3</td><td class="grid">FP_MUL</td></tr>
<tr><td class="grid"><code>IMUL</code></td><td class="grid">-/15-18/4</td><td class="grid">-/5</td><td class="grid">-</td></tr>
</table>
</object>
</div>
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>IN: Input from Port (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>IN: Input from Port (x86 Instruction Set Reference)</title>
<h1>IN</h1>
<h2>Input from Port</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>E4 ib</code></td>
<td class="grid"><code>IN AL,imm8</code></td>
<td class="grid">Input byte from imm8 I/O port address into AL.</td>
</tr>
<tr>
<td class="grid"><code>E5 ib</code></td>
<td class="grid"><code>IN AX,imm8</code></td>
<td class="grid">Input byte from imm8 I/O port address into AX.</td>
</tr>
<tr>
<td class="grid"><code>E5 ib</code></td>
<td class="grid"><code>IN EAX,imm8</code></td>
<td class="grid">Input byte from imm8 I/O port address into EAX.</td>
</tr>
<tr>
<td class="grid"><code>EC</code></td>
<td class="grid"><code>IN AL,DX</code></td>
<td class="grid">Input byte from I/O port in DX into AL.</td>
</tr>
<tr>
<td class="grid"><code>ED</code></td>
<td class="grid"><code>IN AX,DX</code></td>
<td class="grid">Input word from I/O port in DX into AX.</td>
</tr>
<tr>
<td class="grid"><code>ED</code></td>
<td class="grid"><code>IN EAX,DX</code></td>
<td class="grid">Input doubleword from I/O port in DX into EAX.</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Copies the value from the I/O port specified with the second operand (source operand) to the destination operand (first operand). The source operand can be a byte-immediate or the DX register; the destination operand can be register AL, AX, or EAX, depending on the size of the port being accessed (8, 16, or 32 bits, respectively). Using the DX register as a source operand allows I/O port addresses from 0 to 65,535 to be accessed; using a byte immediate allows I/O port addresses 0 to 255 to be accessed.</p>
<p>When accessing an 8-bit I/O port, the opcode determines the port size; when accessing a 16- and 32-bit I/O port, the operand-size attribute determines the port size.</p>
<p>At the machine code level, I/O instructions are shorter when accessing 8-bit I/O ports. Here, the upper eight bits of the port address will be 0.</p>
<p>This instruction is only useful for accessing I/O ports located in the processor's I/O address space. See Chapter 13, Input/Output, in the IA-32 Intel Architecture Software Developer's Manual, Volume 1, for more information on accessing I/O ports in the I/O address space.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre><span class="keyword">if</span><span class="operator">(</span>PE <span class="operator">==</span> <span class="number">1</span> <span class="operator">&amp;&amp;</span> CPL <span class="operator">&gt;</span> IOPL <span class="operator">||</span> VM <span class="operator">==</span> <span class="number">1</span><span class="operator">)</span> { <span class="comment">//Protected mode with CPL > IOPL or virtual-8086 mode</span>
	<span class="keyword">if</span><span class="operator">(</span>AnyPermissionBitSet<span class="operator">(</span>CurrentIOPort<span class="operator">(</span><span class="operator">)</span><span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>GP<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span> <span class="comment">//If any I/O Permission Bit for I/O port being accessed == 1 the I/O operation is not allowed</span>
	<span class="keyword">else</span> Destination <span class="operator">=</span> Source<span class="operator">;</span> <span class="comment">//I/O operation is allowed; Reads from selected I/O port</span>
}
<span class="keyword">else</span> Destination <span class="operator">=</span> Source<span class="operator">;</span> <span class="comment">//Real Mode or Protected Mode with CPL <= IOPL; Reads from selected I/O port</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If the CPL is greater than (has less privilege) the I/O privilege level (IOPL) and any of the corresponding I/O permission bits in TSS for the I/O port being accessed is 1.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
None.
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If any of the I/O permission bits in the TSS for the I/O port being accessed is 1.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Instruction</th>
<th>Latency</th>
<th>Throughput</th>
<th>Execution Unit</th>
</tr>
<tr><td class="grid"><code>CPUID</code></td><td class="grid">0F3n/0F2n/069n</td><td class="grid">0F3n/0F2n/069n</td><td class="grid">0F2n</td></tr>
<tr><td class="grid"><code>IN</code></td><td class="grid">&lt;225</td><td class="grid">40</td><td class="grid">-</td></tr>
</table>
</object>
</div>
</body>
</html>

Added doc/x86/html/file_module_x86_id_14.html.











































































































































































































































































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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>ANDPS: Bitwise Logical AND of Packed Single-Precision Floating-Point Values (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>ANDPS: Bitwise Logical AND of Packed Single-Precision Floating-Point Values (x86 Instruction Set Reference)</title>
<h1>ANDPS</h1>
<h2>Bitwise Logical AND of Packed Single-Precision Floating-Point Values</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>0F 54 /r</code></td>
<td class="grid"><code>ANDPS xmm1, xmm2/m128</code></td>
<td class="grid">Bitwise logical AND of xmm2/m128 and xmm1.</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Performs a bitwise logical AND of the four packed single-precision floating-point values from the source operand (second operand) and the destination operand (first operand), and stores the result in the destination operand. The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre>Destination<span class="operator">[</span><span class="number">0..127</span><span class="operator">]</span> <span class="operator">=</span> Destination<span class="operator">[</span><span class="number">0..127</span><span class="operator">]</span> <span class="operator">&amp;</span> Source<span class="operator">[</span><span class="number">0..127</span><span class="operator">]</span><span class="operator">;</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>SIMD Floating-Point Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
None.
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#GP(0)</code></td><td>For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments. If a memory operand is not aligned on a 16-byte boundary, regardless of segment.</td></tr>
<tr><td><code>#SS(0)</code></td><td>For an illegal address in the SS segment.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>For a page fault.</td></tr>
<tr><td><code>#NM</code></td><td>If TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If a memory operand is not aligned on a 16-byte boundary, regardless of segment. If any part of the operand lies outside the effective address space from 0 to FFFFH.</td></tr>
<tr><td><code>#NM</code></td><td>If TS in CR0 is set.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
Same exceptions as in Real Address Mode
<div>
<table class="operations_table">
<tr><td><code>#PF(fault-code)</code></td><td>For a page fault.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Instruction</th>
<th>Latency</th>
<th>Throughput</th>
<th>Execution Unit</th>
</tr>
<tr><td class="grid"><code>CPUID</code></td><td class="grid">0F3n/0F2n/069n</td><td class="grid">0F3n/0F2n/069n</td><td class="grid">0F2n</td></tr>
<tr><td class="grid"><code>ANDPS xmm, xmm</code></td><td class="grid">4/4/2</td><td class="grid">2/2/2</td><td class="grid">MMX_ALU</td></tr>
</table>
</object>
</div>
</body>
</html>

Added doc/x86/html/file_module_x86_id_140.html.





















































































































































































































































































































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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>INC: Increment by 1 (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>INC: Increment by 1 (x86 Instruction Set Reference)</title>
<h1>INC</h1>
<h2>Increment by 1</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>FE /0</code></td>
<td class="grid"><code>INC r/m8</code></td>
<td class="grid">Increment r/m byte by 1.</td>
</tr>
<tr>
<td class="grid"><code>FF /0</code></td>
<td class="grid"><code>INC r/m16</code></td>
<td class="grid">Increment r/m word by 1.</td>
</tr>
<tr>
<td class="grid"><code>FF /0</code></td>
<td class="grid"><code>INC r/m32</code></td>
<td class="grid">Increment r/m doubleword by 1.</td>
</tr>
<tr>
<td class="grid"><code>40+ rw</code></td>
<td class="grid"><code>INC r16</code></td>
<td class="grid">Increment word register by 1.</td>
</tr>
<tr>
<td class="grid"><code>40+ rd</code></td>
<td class="grid"><code>INC r32</code></td>
<td class="grid">Increment doubleword register by 1.</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Adds 1 to the destination operand, while preserving the state of the CF flag. The destination operand can be a register or a memory location. This instruction allows a loop counter to be updated without disturbing the CF flag. (Use a ADD instruction with an immediate operand of 1 to perform an increment operation that does updates the CF flag.) This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre>Destination <span class="operator">=</span> Destination <span class="operator">+</span> <span class="number">1</span><span class="operator">;</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>The CF flag is not affected. The OF, SF, ZF, AF, and PF flags are set according to the result.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If the destination operand is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If the destination operand is located in a non-writable segment. If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the DS, ES, FS, or GS register is used to access memory and it contains a null segment selector.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#GP</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If a memory operand effective address is outside the SS segment limit.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Instruction</th>
<th>Latency</th>
<th>Throughput</th>
<th>Execution Unit</th>
</tr>
<tr><td class="grid"><code>CPUID</code></td><td class="grid">0F3n/0F2n</td><td class="grid">0F3n/0F2n</td><td class="grid">0F2n</td></tr>
<tr><td class="grid"><code>INC</code></td><td class="grid">1/1</td><td class="grid">0.5/0.5</td><td class="grid">ALU</td></tr>
</table>
</object>
</div>
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>INS/INSB/INSW/INSD: Input from Port to String (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>INS/INSB/INSW/INSD: Input from Port to String (x86 Instruction Set Reference)</title>
<h1>INS/INSB/INSW/INSD</h1>
<h2>Input from Port to String</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>6C INS m8, DX</code></td>
<td class="grid"><code>Input byte from I/O port specified in DX into memory location specified in ES:(E)DI.</code></td>
<td class="grid"></td>
</tr>
<tr>
<td class="grid"><code>6D INS m16, DX</code></td>
<td class="grid"><code>Input word from I/O port specified in DX into memory location specified in ES:(E)DI.</code></td>
<td class="grid"></td>
</tr>
<tr>
<td class="grid"><code>6D INS m32, DX</code></td>
<td class="grid"><code>Input doubleword from I/O port specified in DX into memory location specified in ES:(E)DI.</code></td>
<td class="grid"></td>
</tr>
<tr>
<td class="grid"><code>6C INSB</code></td>
<td class="grid"><code>Input byte from I/O port specified in DX into memory location specified with ES:(E)DI.</code></td>
<td class="grid"></td>
</tr>
<tr>
<td class="grid"><code>6D INSW</code></td>
<td class="grid"><code>Input word from I/O port specified in DX into memory location specified in ES:(E)DI.</code></td>
<td class="grid"></td>
</tr>
<tr>
<td class="grid"><code>6D INSD</code></td>
<td class="grid"><code>Input doubleword from I/O port specified in DX into memory location specified in ES:(E)DI.</code></td>
<td class="grid"></td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Copies the data from the I/O port specified with the source operand (second operand) to the destination operand (first operand). The source operand is an I/O port address (from 0 to 65,535) that is read from the DX register. The destination operand is a memory location, the address of which is read from either the ES:EDI or the ES:DI registers (depending on the address-size attribute of the instruction, 32 or 16, respectively). (The ES segment cannot be overridden with a segment override prefix.) The size of the I/O port being accessed (that is, the size of the source and destination operands) is determined by the opcode for an 8-bit I/O port or by the operandsize attribute of the instruction for a 16- or 32-bit I/O port.</p>
<p>At the assembly-code level, two forms of this instruction are allowed: the &quot;explicit-operands&quot; form and the &quot;no-operands&quot; form. The explicit-operands form (specified with the INS mnemonic) allows the source and destination operands to be specified explicitly. Here, the source operand must be &quot;DX,&quot; and the destination operand should be a symbol that indicates the size of the I/O port and the destination address. This explicit-operands form is provided to allow documentation; however, note that the documentation provided by this form can be misleading.</p>
<p>That is, the destination operand symbol must specify the correct type (size) of the operand (byte, word, or doubleword), but it does not have to specify the correct location. The location is always specified by the ES:(E)DI registers, which must be loaded correctly before the INS instruction is executed.</p>
<p>The no-operands form provides &quot;short forms&quot; of the byte, word, and doubleword versions of the INS instructions. Here also DX is assumed by the processor to be the source operand and ES:(E)DI is assumed to be the destination operand. The size of the I/O port is specified with the choice of mnemonic: INSB (byte), INSW (word), or INSD (doubleword).</p>
<p>After the byte, word, or doubleword is transfer from the I/O port to the memory location, the (E)DI register is incremented or decremented automatically according to the setting of the DF flag in the EFLAGS register. (If the DF flag is 0, the (E)DI register is incremented; if the DF flag is 1, the (E)DI register is decremented.) The (E)DI register is incremented or decremented by 1 for byte operations, by 2 for word operations, or by 4 for doubleword operations.</p>
<p>The INS, INSB, INSW, and INSD instructions can be preceded by the REP prefix for block input of ECX bytes, words, or doublewords. See &quot;REP/REPE/REPZ/REPNE /REPNZ-Repeat String Operation Prefix&quot; in this chapter for a description of the REP prefix.</p>
<p>These instructions are only useful for accessing I/O ports located in the processor's I/O address space. See Chapter 13, Input/Output, in the IA-32 Intel Architecture Software Developer's Manual, Volume 1, for more information on accessing I/O ports in the I/O address space.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre><span class="keyword">if</span><span class="operator">(</span>PE <span class="operator">==</span> <span class="number">1</span> <span class="operator">&amp;&amp;</span> CPL <span class="operator">&gt;</span> IOPL <span class="operator">||</span> VM <span class="operator">==</span> <span class="number">1</span><span class="operator">)</span> { <span class="comment">//Protected mode with CPL > IOPL or virtual-8086 mode</span>
	<span class="keyword">if</span><span class="operator">(</span>AnyPermissionBitSet<span class="operator">(</span>CurrentIOPort<span class="operator">(</span><span class="operator">)</span><span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>GP<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span> <span class="comment">//If any I/O Permission Bit for I/O port being accessed == 1 the I/O operation is not allowed</span>
	<span class="keyword">else</span> Destination <span class="operator">=</span> Source<span class="operator">;</span> <span class="comment">//I/O operation is allowed; Reads from selected I/O port</span>
}
<span class="keyword">else</span> Destination <span class="operator">=</span> Source<span class="operator">;</span> <span class="comment">//Real Mode or Protected Mode with CPL <= IOPL; Reads from selected I/O port</span>

<span class="keyword">if</span><span class="operator">(</span>IsByteTransfer<span class="operator">(</span><span class="operator">)</span><span class="operator">)</span> {
	<span class="keyword">if</span><span class="operator">(</span>DF <span class="operator">==</span> <span class="number">0</span><span class="operator">)</span> <span class="operator">(</span>E<span class="operator">)</span>DI <span class="operator">=</span> <span class="operator">(</span>E<span class="operator">)</span>DI <span class="operator">+</span> <span class="number">1</span><span class="operator">;</span>
	<span class="keyword">else</span> <span class="operator">(</span>E<span class="operator">)</span>DI <span class="operator">=</span> <span class="operator">(</span>E<span class="operator">)</span>DI <span class="operator">-</span> <span class="number">1</span><span class="operator">;</span>
}
<span class="keyword">else</span> <span class="keyword">if</span><span class="operator">(</span>IsWordTransfer<span class="operator">(</span><span class="operator">)</span><span class="operator">)</span> {
	<span class="keyword">if</span><span class="operator">(</span>DF <span class="operator">==</span> <span class="number">0</span><span class="operator">)</span> <span class="operator">(</span>E<span class="operator">)</span>DI <span class="operator">=</span> <span class="operator">(</span>E<span class="operator">)</span>DI <span class="operator">+</span> <span class="number">2</span><span class="operator">;</span>
	<span class="keyword">else</span> <span class="operator">(</span>E<span class="operator">)</span>DI <span class="operator">=</span> <span class="operator">(</span>E<span class="operator">)</span>DI <span class="operator">-</span> <span class="number">2</span><span class="operator">;</span>
}
<span class="keyword">else</span> { <span class="comment">//doubleword transfer</span>
	<span class="keyword">if</span><span class="operator">(</span>DF <span class="operator">==</span> <span class="number">0</span><span class="operator">)</span> <span class="operator">(</span>E<span class="operator">)</span>DI <span class="operator">=</span> <span class="operator">(</span>E<span class="operator">)</span>DI <span class="operator">+</span> <span class="number">4</span><span class="operator">;</span>
	<span class="keyword">else</span> <span class="operator">(</span>E<span class="operator">)</span>DI <span class="operator">=</span> <span class="operator">(</span>E<span class="operator">)</span>DI <span class="operator">-</span> <span class="number">4</span><span class="operator">;</span>
}
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>None.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If the CPL is greater than (has less privilege) the I/O privilege level (IOPL) and any of the corresponding I/O permission bits in TSS for the I/O port being accessed is 1. If the destination is located in a non-writable segment. If an illegal memory operand effective address in the ES segments is given.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If the CPL is greater than (has less privilege) the I/O privilege level (IOPL) and any of the corresponding I/O permission bits in TSS for the I/O port being accessed is 1. If the destination is located in a non-writable segment. If an illegal memory operand effective address in the ES segments is given.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr><td><code>#GP</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If any of the I/O permission bits in the TSS for the I/O port being accessed is 1.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If any of the I/O permission bits in the TSS for the I/O port being accessed is 1.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
</div>
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>INT n/INTO/INT 3: Call to Interrupt Procedure (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>INT n/INTO/INT 3: Call to Interrupt Procedure (x86 Instruction Set Reference)</title>
<h1>INT n/INTO/INT 3</h1>
<h2>Call to Interrupt Procedure</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>CC</code></td>
<td class="grid"><code>INT 3</code></td>
<td class="grid">Interrupt 3 - trap to debugger.</td>
</tr>
<tr>
<td class="grid"><code>CD ib</code></td>
<td class="grid"><code>INT imm8</code></td>
<td class="grid">Interrupt vector number specified by immediate byte.</td>
</tr>
<tr>
<td class="grid"><code>CE</code></td>
<td class="grid"><code>INTO</code></td>
<td class="grid">Interrupt 4 - if overflow flag is 1.</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>The INT n instruction generates a call to the interrupt or exception handler specified with the destination operand (see the section titled &quot;Interrupts and {exceptions}&quot; in Chapter 6 of the IA-32 Intel Architecture Software Developer's Manual, Volume 1). The destination operand specifies an interrupt vector number from 0 to 255, encoded as an 8-bit unsigned intermediate value. Each interrupt vector number provides an index to a gate descriptor in the IDT. The first 32 interrupt vector numbers are reserved by Intel for system use. Some of these interrupts are used for internally generated exceptions.</p>
<p>The INT n instruction is the general mnemonic for executing a software-generated call to an interrupt handler. The INTO instruction is a special mnemonic for calling overflow exception (#OF), interrupt vector number 4. The overflow interrupt checks the OF flag in the EFLAGS register and calls the overflow interrupt handler if the OF flag is set to 1.</p>
<p>The INT 3 instruction generates a special one byte opcode (CC) that is intended for calling the debug exception handler. (This one byte form is valuable because it can be used to replace the first byte of any instruction with a breakpoint, including other one byte instructions, without over-writing other code). To further support its function as a debug breakpoint, the interrupt generated with the CC opcode also differs from the regular software interrupts as follows: - Interrupt redirection does not happen when in VME mode; the interrupt is handled by a protected-mode handler.</p>
<p>The virtual-8086 mode IOPL checks do not occur. The interrupt is taken without faulting at any IOPL level.</p>
<p>Note that the &quot;normal&quot; 2-byte opcode for INT 3 (CD03) does not have these special features.</p>
<p>Intel and Microsoft assemblers will not generate the CD03 opcode from any mnemonic, but this opcode can be created by direct numeric code definition or by self-modifying code.</p>
<p>The action of the INT n instruction (including the INTO and INT 3 instructions) is similar to that of a far call made with the CALL instruction. The primary difference is that with the INT n instruction, the EFLAGS register is pushed onto the stack before the return address. (The return address is a far address consisting of the current values of the CS and EIP registers.) Returns from interrupt procedures are handled with the IRET instruction, which pops the EFLAGS information and return address from the stack.</p>
<p>The interrupt vector number specifies an interrupt descriptor in the interrupt descriptor table (IDT); that is, it provides index into the IDT. The selected interrupt descriptor in turn contains a pointer to an interrupt or exception handler procedure. In protected mode, the IDT contains an array of 8-byte descriptors, each of which is an interrupt gate, trap gate, or task gate. In realaddress mode, the IDT is an array of 4-byte far pointers (2-byte code segment selector and a 2-byte instruction pointer), each of which point directly to a procedure in the selected segment.</p>
<p>(Note that in real-address mode, the IDT is called the interrupt vector table, and its pointers are called interrupt vectors.)</p>
<p>The following decision table indicates which action in the lower portion of the table is taken given the conditions in the upper portion of the table. Each Y in the lower section of the decision table represents a procedure defined in the &quot;Operation&quot; section for this instruction (except #GP).</p>
<div>
<table class="grid">
<caption>Decision Table</caption>
<tr><td>PE</td><td>0</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
<tr><td>VM</td><td>Don't care</td><td>Don't care</td><td>Don't care</td><td>Don't care</td><td>Don't care</td><td>0</td><td>1</td><td>1</td></tr>
<tr><td>IOPL</td><td>Don't care</td><td>Don't care</td><td>Don't care</td><td>Don't care</td><td>Don't care</td><td>Don't care</td><td>&lt;3</td><td>=3</td></tr>
<tr><td>DPL/CPL RELATIONSHIP</td><td>Don't care</td><td>DPL &lt; CPL</td><td>Don't care</td><td>DPL &gt; CPL</td><td>DPL = CPL or C</td><td>DPL &lt; CPL &amp; NC</td><td>Don't care</td><td>Don't care</td></tr>
<tr><td>INTERRUPT TYPE</td><td>Don't care</td><td>S/W</td><td>Don't care</td><td>Don't care</td><td>Don't care</td><td>Don't care</td><td>Don't care</td><td>Don't care</td></tr>
<tr><td>GATE TYPE</td><td>Don't care</td><td>Don't care</td><td>Task Trap or Interrupt</td><td>Trap or Interrupt</td><td>Trap or Interrupt</td><td>Trap or Interrupt</td><td>Trap or Interrupt</td></tr>
<tr><td>REAL-ADDRESS-MODE</td><td>Action taken</td><td>No action</td><td>No action</td><td>No action</td><td>No action</td><td>No action</td><td>No action</td><td>No action</td></tr>
<tr><td>PROTECTED-MODE</td><td>No action</td><td>Action taken</td><td>Action taken</td><td>Action taken</td><td>Action taken</td><td>Action taken</td><td>Action taken</td><td>Action taken</td></tr>
<tr><td>TRAP-OR-INTERRUPT-GATE</td><td>No action</td><td>No action</td><td>No action</td><td>Action taken</td><td>Action taken</td><td>Action taken</td><td>Action taken</td><td>Action taken</td></tr>
<tr><td>INTER-PRIVILEGE-LEVEL-INTERRUPT</td><td>No action</td><td>No action</td><td>No action</td><td>No action</td><td>No action</td><td>Action taken</td><td>No action</td><td>No action</td></tr>
<tr><td>INTRA-PRIVILEGE-LEVEL-INTERRUPT</td><td>No action</td><td>No action</td><td>No action</td><td>No action</td><td>Action taken</td><td>No action</td><td>No action</td><td>No action</td></tr>
<tr><td>INTERRUPT-FROM-VIRTUAL-8086-MODE</td><td>No action</td><td>No action</td><td>No action</td><td>No action</td><td>No action</td><td>No action</td><td>No action</td><td>Action taken</td></tr>
<tr><td>TASK-GATE</td><td>No action</td><td>No action</td><td>Action taken</td><td>No action</td><td>No action</td><td>No action</td><td>No action</td><td>No action</td></tr>
<tr><td>#GP</td><td>No action</td><td>Action taken</td><td>No action</td><td>Action taken</td><td>No action</td><td>No action</td><td>Action taken</td><td>No action</td></tr>
</table>
</div>
<p>When the processor is executing in virtual-8086 mode, the IOPL determines the action of the INT n instruction. If the IOPL is less than 3, the processor generates a general protection exception (#GP); if the IOPL is 3, the processor executes a protected mode interrupt to privilege level 0. The interrupt gate's DPL must be set to 3 and the target CPL of the interrupt handler procedure must be 0 to execute the protected mode interrupt to privilege level 0.</p>
<p>The interrupt descriptor table register (IDTR) specifies the base linear address and limit of the IDT. The initial base address value of the IDTR after the processor is powered up or reset is 0.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre><span class="comment">//The following operational description applies not only to the INT n and INTO instructions, but also to external interrupts and exceptions.</span>
<span class="keyword">if</span><span class="operator">(</span>pe <span class="operator">==</span> <span class="number">0</span><span class="operator">)</span> {
	<span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IsWithinIDTLimit<span class="operator">(</span>Destination <span class="operator">*</span> <span class="number">4</span> <span class="operator">+</span> <span class="number">3</span><span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>GP<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
	<span class="keyword">if</span><span class="operator">(</span>GetStackSpace<span class="operator">(</span><span class="operator">)</span> <span class="operator">&lt;</span> <span class="number">6</span><span class="operator">)</span> Exception<span class="operator">(</span>SS<span class="operator">)</span><span class="operator">;</span>
	Push<span class="operator">(</span>EFLAGS<span class="operator">[</span><span class="number">0..15</span><span class="operator">]</span><span class="operator">)</span><span class="operator">;</span>
	IF <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
	TF <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
	AC <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
	Push<span class="operator">(</span>CS<span class="operator">)</span><span class="operator">;</span>
	Push<span class="operator">(</span>IP<span class="operator">)</span><span class="operator">;</span>
	CS <span class="operator">=</span> IDT<span class="operator">(</span>Descriptor<span class="operator">(</span>VectorNumber <span class="operator">*</span> <span class="number">4</span><span class="operator">)</span><span class="operator">,</span> Selector<span class="operator">)</span><span class="operator">;</span>
	EIP <span class="operator">=</span> IDT<span class="operator">(</span>Descriptor<span class="operator">(</span>VectorNumber <span class="operator">*</span> <span class="number">4</span><span class="operator">)</span><span class="operator">,</span> Offset<span class="operator">)</span><span class="operator">;</span> <span class="comment">//16 bit offset & 0xFFFF</span>
}
<span class="keyword">else</span> {
	<span class="keyword">if</span><span class="operator">(</span>VM <span class="operator">==</span> <span class="number">1</span> <span class="operator">&amp;&amp;</span> IOPL <span class="operator">&lt;</span> <span class="number">3</span> <span class="operator">&amp;&amp;</span> INT<span class="operator">(</span>n<span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>GP<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
	<span class="keyword">else</span> { <span class="comment">//protected mode or virtual-8086 mode interrupt</span>
		<span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IsWithinIDTLimits<span class="operator">(</span>Destination <span class="operator">*</span> <span class="number">8</span> <span class="operator">+</span> <span class="number">7</span><span class="operator">)</span> <span class="operator">||</span> <span class="operator">!</span><span class="operator">(</span>GetCurrentIDTDescriptorType<span class="operator">(</span><span class="operator">)</span> <span class="operator">&amp;</span> <span class="operator">(</span>TYPE_INTERRUPT <span class="operator">|</span> TYPE_TRAP <span class="operator">|</span> TYPE_TASK_GATE<span class="operator">)</span><span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>GP<span class="operator">(</span>Destination <span class="operator">*</span> <span class="number">8</span> <span class="operator">+</span> <span class="number">2</span> <span class="operator">+</span> EXT<span class="operator">)</span><span class="operator">)</span><span class="operator">;</span> <span class="comment">//Selected IDT descriptor is not an iterrupt-, trap-, or task-gate type; EXT is bit 0 in error code</span>
		<span class="keyword">if</span><span class="operator">(</span>IsSoftwareInterrupt<span class="operator">(</span><span class="operator">)</span> <span class="comment">/*generated by INT n, INT 3, or INTO*/</span> <span class="operator">&amp;&amp;</span> GateDescriptor<span class="operator">.</span>DPL <span class="operator">&lt;</span> CPL<span class="operator">)</span> Exception<span class="operator">(</span>GP<span class="operator">(</span>VectorNumber <span class="operator">*</span> <span class="number">8</span> <span class="operator">+</span> <span class="number">2</span><span class="operator">)</span><span class="operator">;</span> <span class="comment">//PE = 1, DPL < CPL, software interrupt</span>
		<span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IsPresent<span class="operator">(</span>Gate<span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>NP<span class="operator">(</span>VectorNumber <span class="operator">*</span> <span class="number">8</span> <span class="operator">+</span> <span class="number">2</span> <span class="operator">+</span> EXT<span class="operator">)</span><span class="operator">;</span>
		<span class="keyword">if</span><span class="operator">(</span>IsTaskGate<span class="operator">(</span><span class="operator">)</span><span class="operator">)</span> {
			<span class="comment">//Task-gate</span>
			<span class="comment">//PE = 1, task gate</span>
			IDTDescriptor <span class="operator">=</span> ReadSegmentSelector<span class="operator">(</span>TaskGate<span class="operator">)</span><span class="operator">;</span>
			<span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IsGlobal<span class="operator">(</span><span class="operator">)</span> <span class="operator">||</span> <span class="operator">!</span>IsWithinGDTLimits<span class="operator">(</span>Index<span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>GP<span class="operator">(</span>TSSSelector<span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
			TSSDescriptor <span class="operator">=</span> AccessTSSDescriptor<span class="operator">(</span>GDT<span class="operator">.</span>TSSDescriptor<span class="operator">)</span><span class="operator">;</span>
			<span class="keyword">if</span><span class="operator">(</span>TSSIsBusy<span class="operator">(</span>TSSDescriptor<span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>GP<span class="operator">(</span>TSSSelector<span class="operator">)</span><span class="operator">)</span><span class="operator">;</span> <span class="comment">//TSS descriptor specifies that the TSS is busy (low-order 5 bits set to 00001)</span>
			<span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IsPresent<span class="operator">(</span>TSSDescriptor<span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>NP<span class="operator">(</span>TSSSelector<span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
			SwitchTasks<span class="operator">(</span>TSSDescriptor<span class="operator">,</span> WithNesting<span class="operator">)</span><span class="operator">;</span> <span class="comment">//Switch tasks (with nesting) to TSS</span>
			<span class="keyword">if</span><span class="operator">(</span>InterruptOccured<span class="operator">(</span><span class="operator">)</span><span class="operator">)</span> { <span class="comment">//interrupt caused by fault with error code</span>
				<span class="keyword">if</span><span class="operator">(</span>GetStackSpace<span class="operator">(</span><span class="operator">)</span> <span class="operator">&lt;</span> ErrorCodeSize<span class="operator">)</span> Exception<span class="operator">(</span>SS<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span> <span class="comment">//stack limit does not allow push of error code</span>
				Push<span class="operator">(</span>ErrorCode<span class="operator">)</span><span class="operator">;</span>
			}
			<span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IsWithinCSLimit<span class="operator">(</span>EIP<span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>GP<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
		}
		<span class="keyword">else</span> { <span class="comment">//PE = 1, trap/interrupt gate</span>
			<span class="comment">//Trap interrupt gate</span>
			IDTDescriptor <span class="operator">=</span> ReadSegmentSelector<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span>
			<span class="keyword">if</span><span class="operator">(</span>CodeSegmentSelector <span class="operator">==</span> <span class="number">0</span><span class="operator">)</span> Exception<span class="operator">(</span>GP<span class="operator">(</span><span class="number">0</span> <span class="operator">+</span> EXT<span class="operator">)</span><span class="operator">)</span><span class="operator">;</span> <span class="comment">//null selector with EXT flag set</span>
			<span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IsWithinDescriptorTableLimits<span class="operator">(</span>SegmentSelector<span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>GP<span class="operator">(</span>SegmentSelector <span class="operator">+</span> EXT<span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
			Descriptor <span class="operator">=</span> ReadDescriptor<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span> <span class="comment">//Read trap or interrupt handler descriptor</span>
			<span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IndicatesCodeSegment<span class="operator">(</span>Descriptor<span class="operator">)</span> <span class="operator">||</span> CodeSegmentDescriptor<span class="operator">.</span>DPL <span class="operator">&gt;</span> CPL<span class="operator">)</span> Exception<span class="operator">(</span>GP<span class="operator">(</span>Selector <span class="operator">+</span> EXT<span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
			<span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IsPresent<span class="operator">(</span>GateSegment<span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>NP<span class="operator">(</span>Selector <span class="operator">+</span> EXT<span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
			<span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IsConforming<span class="operator">(</span>CodeSegment<span class="operator">)</span> <span class="operator">&amp;&amp;</span> DPL <span class="operator">&lt;</span> CPL<span class="operator">)</span> {
				<span class="keyword">if</span><span class="operator">(</span>VM <span class="operator">==</span> <span class="number">0</span><span class="operator">)</span> {
					<span class="comment">//Inter-Privilege-Level interrupt</span>
					<span class="comment">//PE == 1, interrupt or trap gate, nonconforming</span>
					<span class="comment">//code segment, DPL < CPL, VM == 0</span>
					<span class="comment">//Check segment selector and descriptor for stack of new privilege level in current TSS</span>
					<span class="keyword">if</span><span class="operator">(</span>Is32BitTSS<span class="operator">(</span>CurrentTSS<span class="operator">)</span><span class="operator">)</span> {
						TSSStackAddress <span class="operator">=</span> NewCodSegment<span class="operator">.</span>DPL <span class="operator">*</span> <span class="number">8</span> <span class="operator">+</span> <span class="number">4</span><span class="operator">;</span>
						<span class="keyword">if</span><span class="operator">(</span>TSSStackAddress <span class="operator">+</span> <span class="number">7</span> <span class="operator">&gt;</span> TSSLim9t<span class="operator">)</span> Exception<span class="operator">(</span>TS<span class="operator">(</span>CurrentTSSSelector<span class="operator">)</span><span class="operator">;</span>
						NewSS <span class="operator">=</span> TSSStackAddress <span class="operator">+</span> <span class="number">4</span><span class="operator">;</span>
						NewESP <span class="operator">=</span> StackAddress<span class="operator">;</span>
					}
					<span class="keyword">else</span> { <span class="comment">//TSS is 16-bit</span>
						TSSStackAddress <span class="operator">=</span> NewCodSegment<span class="operator">.</span>DPL <span class="operator">*</span> <span class="number">4</span> <span class="operator">+</span> <span class="number">2</span><span class="operator">;</span>
						<span class="keyword">if</span><span class="operator">(</span>TSSStackAddress <span class="operator">+</span> <span class="number">4</span> <span class="operator">&gt;</span> TSSLim9t<span class="operator">)</span> Exception<span class="operator">(</span>TS<span class="operator">(</span>CurrentTSSSelector<span class="operator">)</span><span class="operator">;</span>
						NewSS <span class="operator">=</span> TSSStackAddress <span class="operator">+</span> <span class="number">2</span><span class="operator">;</span>
						NewESP <span class="operator">=</span> StackAddress<span class="operator">;</span>
					}
					<span class="keyword">if</span><span class="operator">(</span>SegmentSelector <span class="operator">==</span> <span class="number">0</span><span class="operator">)</span> Exception<span class="operator">(</span>TS<span class="operator">(</span>EXT<span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
					<span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IsWithinDescriptorTableLimits<span class="operator">(</span>SegmentSelector<span class="operator">.</span>Index<span class="operator">)</span> <span class="operator">||</span> SegmentSelector<span class="operator">.</span>RPL <span class="operator">!=</span> CodeSegment<span class="operator">.</span>DPL<span class="operator">)</span> Exception<span class="operator">(</span>TS<span class="operator">(</span>SSSelector <span class="operator">+</span> EXT<span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
					StackSegmentDescriptor <span class="operator">=</span> ReadStackSegmentDescriptor<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span>  <span class="comment">//Read segment descriptor for stack segment in GDT or LDT</span>
					<span class="keyword">if</span><span class="operator">(</span>StackSegment<span class="operator">.</span>DPL <span class="operator">!=</span> CodeSegment<span class="operator">.</span>DPL <span class="operator">||</span> <span class="operator">!</span>IndicatesWritableDataSegment<span class="operator">(</span>StackSegment<span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>TS<span class="operator">(</span>SSSelector <span class="operator">+</span> EXT<span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
					<span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IsPresent<span class="operator">(</span>StackSegment<span class="operator">)</span><span class="operator">)</span> Excpetion<span class="operator">(</span><span class="preprocessor">#SS(SSSelector + EXT));</span>
					<span class="keyword">if</span><span class="operator">(</span>Is32BitGate<span class="operator">(</span><span class="operator">)</span> <span class="operator">&amp;&amp;</span> GetStackSpace<span class="operator">(</span><span class="operator">)</span> <span class="operator">&lt;</span> <span class="number">24</span> <span class="comment">/*error code pushed*/</span> <span class="operator">||</span> GetStackSpace<span class="operator">(</span><span class="operator">)</span> <span class="operator">&lt;</span> <span class="number">20</span> <span class="comment">/*no error code pushed*/</span><span class="operator">)</span> Exception<span class="operator">(</span>SS<span class="operator">(</span>SegmentSelector <span class="operator">+</span> EXT<span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
					<span class="keyword">else</span> <span class="comment">/*16-bit gate*/</span> <span class="keyword">if</span><span class="operator">(</span>GetStackSpace<span class="operator">(</span><span class="operator">)</span> <span class="operator">&lt;</span> <span class="number">12</span> <span class="comment">/*error code pushed*/</span> <span class="operator">||</span> GetStackSpace<span class="operator">(</span><span class="operator">)</span> <span class="operator">&lt;</span> <span class="number">10</span> <span class="comment">/*no error code pushed*/</span><span class="operator">)</span> Exception<span class="operator">(</span>SS<span class="operator">(</span>SegmentSelector <span class="operator">+</span> EXT<span class="operator">)</span><span class="operator">;</span>
					<span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IsWithinCSLimits<span class="operator">(</span>InstructionPointer<span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>GP<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
					SS<span class="operator">:</span>ESP <span class="operator">=</span> TSS<span class="operator">(</span>NewSS<span class="operator">:</span>NewESP<span class="operator">)</span> <span class="comment">//segment descriptor information also loaded</span>
					<span class="keyword">if</span><span class="operator">(</span>Is32BitGate<span class="operator">(</span><span class="operator">)</span><span class="operator">)</span> {
						Push<span class="operator">(</span>FarPointer<span class="operator">(</span>OldStack<span class="operator">)</span><span class="operator">)</span><span class="operator">;</span> <span class="comment">//push a far pointer to the old stack, old SS and ESP, 3 words padded to 4</span>
						Push<span class="operator">(</span>EFLAGS<span class="operator">)</span><span class="operator">;</span>
						Push<span class="operator">(</span>FarPointer<span class="operator">(</span>ReturnInstruction<span class="operator">)</span><span class="operator">)</span><span class="operator">;</span> <span class="comment">//old CS and EIP, 3 words padded to 4</span>
						Push<span class="operator">(</span>ErrorCode<span class="operator">)</span><span class="operator">;</span> <span class="comment">//if needed, 2 bytes</span>
					}
					<span class="keyword">else</span> { <span class="comment">//16-bit gate</span>
						Push<span class="operator">(</span>FarPointer<span class="operator">(</span>OldStack<span class="operator">)</span><span class="operator">)</span><span class="operator">;</span> <span class="comment">//old SS and SP, 2 words</span>
						Push<span class="operator">(</span>EFLAGS<span class="operator">[</span><span class="number">0..15</span><span class="operator">]</span><span class="operator">)</span><span class="operator">;</span>
						Push<span class="operator">(</span>FarPointer<span class="operator">(</span>ReturnInstruction<span class="operator">)</span><span class="operator">)</span><span class="operator">;</span> <span class="comment">//old CS and IP, 2 words</span>
						Push<span class="operator">(</span>ErrorCode<span class="operator">)</span><span class="operator">;</span> <span class="comment">//if needed, 2 bytes</span>
					}
					CPL <span class="operator">=</span> CodeSegmentDescriptor<span class="operator">.</span>DPL<span class="operator">;</span>
					CS<span class="operator">.</span>RPL <span class="operator">=</span> CPL<span class="operator">;</span>
					<span class="keyword">if</span><span class="operator">(</span>IsInterruptGate<span class="operator">(</span><span class="operator">)</span><span class="operator">)</span> IF <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span> <span class="comment">//interrupt flag set to 0: disabled</span>
					TF <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
					VM <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
					RF <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
					NT <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
				}
				<span class="keyword">else</span> { <span class="comment">//VM == 1</span>
					<span class="keyword">if</span><span class="operator">(</span>CodeSegment<span class="operator">.</span>DPL <span class="operator">!=</span> <span class="number">0</span><span class="operator">)</span> Exception<span class="operator">(</span>GP<span class="operator">(</span>NewCodeSegmentSelector<span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
					<span class="comment">//Interrupt from Virtual 8086 mode</span>
					<span class="comment">//PE = 1, interrupt or trap gate, DPL<CPL, VM = 1</span>
					<span class="comment">//Check segment selector and descriptor for privilege level 0 stack in current TSS</span>
					<span class="keyword">if</span><span class="operator">(</span>Is32BitTSS<span class="operator">(</span>CurrentTSS<span class="operator">)</span><span class="operator">)</span> {
						TSSStackAddress <span class="operator">=</span> NewCodeSegment<span class="operator">.</span>DPL <span class="operator">*</span> <span class="number">8</span> <span class="operator">+</span> <span class="number">4</span><span class="operator">;</span>
						<span class="keyword">if</span><span class="operator">(</span>TSSStackAddress <span class="operator">+</span> <span class="number">7</span> <span class="operator">&gt;</span> TSSLimit<span class="operator">)</span> Exception<span class="operator">(</span>TS<span class="operator">(</span>CurrentTSSSelector<span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
						NewSS <span class="operator">=</span> TSSStackAddress <span class="operator">+</span> <span class="number">4</span><span class="operator">;</span>
						NewESP <span class="operator">=</span> StackAddress<span class="operator">;</span>
					}
					<span class="keyword">else</span> { <span class="comment">//TSS is 16-bit</span>
						TSSStackAddress <span class="operator">=</span> NewCodeSegment<span class="operator">.</span>DPL <span class="operator">*</span> <span class="number">4</span> <span class="operator">+</span> <span class="number">2</span><span class="operator">;</span>
						<span class="keyword">if</span><span class="operator">(</span>TSSStackAddress <span class="operator">+</span> <span class="number">4</span> <span class="operator">&gt;</span> TSSLimit<span class="operator">)</span> Excpetion<span class="operator">(</span><span class="preprocessor">#TS(CurrentTSSSelector));</span>
						NewESP <span class="operator">=</span> TSSStackAddress<span class="operator">;</span>
						NewSS <span class="operator">=</span> TSSStackAddress <span class="operator">+</span> <span class="number">2</span><span class="operator">;</span>
					}
					<span class="keyword">if</span><span class="operator">(</span>SegmentSelector <span class="operator">==</span> <span class="number">0</span><span class="operator">)</span> Exception<span class="operator">(</span>TS<span class="operator">(</span>EXT<span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
					<span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IsWithinDescriptorTableLimits<span class="operator">(</span>SegmentSelector<span class="operator">.</span>Index<span class="operator">)</span> <span class="operator">||</span> SegmentSelector<span class="operator">.</span>RPL <span class="operator">!=</span> CodeSegment<span class="operator">.</span>DPL<span class="operator">)</span> Exception<span class="operator">(</span>TS<span class="operator">(</span>SSSelector <span class="operator">+</span> EXT<span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
					<span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IsPresent<span class="operator">(</span>StackSegment<span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>SS<span class="operator">(</span>SSSelector <span class="operator">+</span> EXT<span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
					<span class="keyword">if</span><span class="operator">(</span>Is32BitGate<span class="operator">(</span><span class="operator">)</span> <span class="operator">&amp;&amp;</span> GetStackSpace<span class="operator">(</span><span class="operator">)</span> <span class="operator">&lt;</span> <span class="number">40</span> <span class="comment">/*error code pushed*/</span> <span class="operator">||</span> GetStackSpace<span class="operator">(</span><span class="operator">)</span> <span class="operator">&lt;</span> <span class="number">36</span> <span class="comment">/*no error code pushed*/</span><span class="operator">)</span> Exception<span class="operator">(</span>SS<span class="operator">(</span>SegmentSelector <span class="operator">+</span> EXT<span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
					<span class="keyword">else</span> <span class="comment">/*16-bit gate*/</span> <span class="keyword">if</span><span class="operator">(</span>GetStackSpace<span class="operator">(</span><span class="operator">)</span> <span class="operator">&lt;</span> <span class="number">20</span> <span class="comment">/*error code pushed*/</span> <span class="operator">||</span> GetStackSpace<span class="operator">(</span><span class="operator">)</span> <span class="operator">&lt;</span> <span class="number">18</span> <span class="comment">/*no error code pushed*/</span><span class="operator">)</span> Exception<span class="operator">(</span>SS<span class="operator">(</span>SegmentSelector <span class="operator">+</span> EXT<span class="operator">)</span><span class="operator">;</span>
					<span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IsWithinCodeSegmentLimits<span class="operator">(</span>InstructionPointer<span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>GP<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
					TemporaryEFLAGS <span class="operator">=</span> EFLAGS<span class="operator">;</span>
					VM <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
					TF <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
					RF <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
					NT <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
					<span class="keyword">if</span><span class="operator">(</span>IsInterruptGateService<span class="operator">(</span><span class="operator">)</span><span class="operator">)</span> IF <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span> <span class="comment">//service through interrupt gate</span>
					TemporarySS <span class="operator">=</span> SS<span class="operator">;</span>
					TemporaryESP <span class="operator">=</span> ESP<span class="operator">;</span>
					SS<span class="operator">:</span>ESP <span class="operator">=</span> TSS<span class="operator">(</span>SS0<span class="operator">:</span>ESP0<span class="operator">)</span><span class="operator">;</span> <span class="comment">//Change to level 0 stack segment</span>
					<span class="comment">//Folowing pushes are 16 bits for 16-bit gate and 32 bits for 32-bit gates</span>
					<span class="comment">//Segment selector pushes in 32-bit mode are padded to two words</span>
					Push<span class="operator">(</span>GS<span class="operator">)</span><span class="operator">;</span>
					Push<span class="operator">(</span>FS<span class="operator">)</span><span class="operator">;</span>
					Push<span class="operator">(</span>DS<span class="operator">)</span><span class="operator">;</span>
					Push<span class="operator">(</span>ES<span class="operator">)</span><span class="operator">;</span>
					Push<span class="operator">(</span>TemporarySS<span class="operator">)</span><span class="operator">;</span>
					Push<span class="operator">(</span>TemporaryESP<span class="operator">)</span><span class="operator">;</span>
					Push<span class="operator">(</span>TemporaryEFLAGS<span class="operator">)</span><span class="operator">;</span>
					Push<span class="operator">(</span>CS<span class="operator">)</span><span class="operator">;</span>
					Push<span class="operator">(</span>EIP<span class="operator">)</span><span class="operator">;</span>
					GS <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span> <span class="comment">//segment registers nullified, invalid in protection mode</span>
					FS <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
					DS <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
					ES <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
					CS <span class="operator">=</span> Gate<span class="operator">(</span>CS<span class="operator">)</span><span class="operator">;</span>
					<span class="keyword">if</span><span class="operator">(</span>OperandSize <span class="operator">==</span> <span class="number">32</span><span class="operator">)</span> EIP <span class="operator">=</span> Gate<span class="operator">(</span>InstructionPointer<span class="operator">)</span><span class="operator">;</span>
					<span class="keyword">else</span> EIP <span class="operator">=</span> Gate<span class="operator">(</span>InstructionPointer<span class="operator">)</span> <span class="operator">&amp;</span> <span class="number">0xFFFF</span><span class="operator">;</span> <span class="comment">//OperandSize is 16</span>
					<span class="comment">//Starts execution of new routine in Protected Mode</span>
				}
			}
			<span class="keyword">else</span> { <span class="comment">//PE = 1, interrupt or trap gate, DPL >= CPL</span>
				<span class="keyword">if</span><span class="operator">(</span>VM <span class="operator">==</span> <span class="number">1</span><span class="operator">)</span> Exception<span class="operator">(</span>GP<span class="operator">(</span>NewCodeSegmentSelector<span class="operator">)</span><span class="operator">;</span>
				<span class="keyword">if</span><span class="operator">(</span>IsConforming<span class="operator">(</span>CodeSegment<span class="operator">)</span> <span class="operator">||</span> CodeSegment<span class="operator">.</span>DPL <span class="operator">==</span> CPL<span class="operator">)</span> {
					<span class="comment">//Intra-privilege level interrupt</span>
					<span class="comment">//PE == 1, DPL == CPL or conforming segment</span>
					<span class="keyword">if</span><span class="operator">(</span>Is32BitGate<span class="operator">(</span><span class="operator">)</span> <span class="operator">&amp;&amp;</span> GetStackSpace<span class="operator">(</span><span class="operator">)</span> <span class="operator">&lt;</span> <span class="number">16</span> <span class="comment">/*error code pushed*/</span> <span class="operator">||</span> GetStackSpace<span class="operator">(</span><span class="operator">)</span> <span class="operator">&lt;</span> <span class="number">12</span> <span class="comment">/*no error code pushed*/</span><span class="operator">)</span> Exception<span class="operator">(</span>SS<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
					<span class="keyword">else</span> <span class="comment">/*16-bit gate*/</span> <span class="keyword">if</span><span class="operator">(</span>GetStackSpace<span class="operator">(</span><span class="operator">)</span> <span class="operator">&lt;</span> <span class="number">8</span> <span class="comment">/*error code pushed*/</span> <span class="operator">||</span> GetStackSpace<span class="operator">(</span><span class="operator">)</span> <span class="operator">&lt;</span> <span class="number">6</span> <span class="comment">/*no error code pushed*/</span><span class="operator">)</span> Exception<span class="operator">(</span>SS<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">;</span>
					<span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IsWithinCodeSegmentLimit<span class="operator">(</span>InstructionPointer<span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>GP<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
					<span class="keyword">if</span><span class="operator">(</span>Is32BitGate<span class="operator">(</span><span class="operator">)</span><span class="operator">)</span> {
						Push<span class="operator">(</span>EFLAGS<span class="operator">)</span><span class="operator">;</span>
						Push<span class="operator">(</span>FarPointer<span class="operator">(</span>ReturnInstruction<span class="operator">)</span><span class="operator">)</span><span class="operator">;</span> <span class="comment">//3 words padded to 4</span>
						CS<span class="operator">:</span>EIP <span class="operator">=</span> Gate<span class="operator">(</span>CS<span class="operator">:</span>EIP<span class="operator">)</span><span class="operator">;</span> <span class="comment">//segment descriptor information also loaded</span>
						Push<span class="operator">(</span>ErrorCode<span class="operator">)</span><span class="operator">;</span> <span class="comment">//if any</span>
					}
					<span class="keyword">else</span> { <span class="comment">//16-bit gate</span>
						Push<span class="operator">(</span>FLAGS<span class="operator">)</span><span class="operator">;</span>
						Push<span class="operator">(</span>FarPointer<span class="operator">(</span>ReturnLocation<span class="operator">)</span><span class="operator">)</span><span class="operator">;</span> <span class="comment">//2 words</span>
						CS<span class="operator">:</span>IP <span class="operator">=</span> Gate<span class="operator">(</span>CS<span class="operator">:</span>IP<span class="operator">)</span><span class="operator">;</span> <span class="comment">//segment descriptor information also loaded</span>
						Push<span class="operator">(</span>ErrorCode<span class="operator">)</span><span class="operator">;</span> <span class="comment">//if any</span>
					}
					CS<span class="operator">.</span>RPL <span class="operator">=</span> CPL<span class="operator">;</span>
					<span class="keyword">if</span><span class="operator">(</span>IsInterruptGate<span class="operator">(</span><span class="operator">)</span><span class="operator">)</span> IF <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span> <span class="comment">//interrupt flag is set to 0: disabled</span>
					TF <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
					NT <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
					VM <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
					RF <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span>
				}
				<span class="keyword">else</span> Exception<span class="operator">(</span>GP<span class="operator">(</span>CodeSegmentSelector <span class="operator">+</span> EXT<span class="operator">)</span><span class="operator">;</span>
			}
		}
	}
}
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>The EFLAGS register is pushed onto the stack. The IF, TF, NT, AC, RF, and VM flags may be cleared, depending on the mode of operation of the processor when the INT instruction is executed (see the &quot;Operation&quot; section). If the interrupt uses a task gate, any flags may be set or cleared, controlled by the EFLAGS image in the new task's TSS.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If the instruction pointer in the IDT or in the interrupt-, trap-, or task gate is beyond the code segment limits.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If the instruction pointer in the IDT or in the interrupt-, trap-, or task gate is beyond the code segment limits.</td></tr>
<tr><td><code>#GP(selector)</code></td><td>If the segment selector in the interrupt-, trap-, or task gate is null. If an interrupt-, trap-, or task gate, code segment, or TSS segment selector index is outside its descriptor table limits. If the interrupt vector number is outside the IDT limits. If an IDT descriptor is not an interrupt-, trap-, or task-descriptor. If an interrupt is generated by the INT n, INT 3, or INTO instruction and the DPL of an interrupt-, trap-, or task-descriptor is less than the CPL. If the segment selector in an interrupt- or trap-gate does not point to a segment descriptor for a code segment. If the segment selector for a TSS has its local/global bit set for local. If a TSS segment descriptor specifies that the TSS is busy or not available.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If pushing the return address, flags, or error code onto the stack exceeds the bounds of the stack segment and no stack switch occurs.</td></tr>
<tr><td><code>#SS(selector)</code></td><td>If the SS register is being loaded and the segment pointed to is marked not present. If pushing the return address, flags, error code, or stack segment pointer exceeds the bounds of the new stack segment when a stack switch occurs.</td></tr>
<tr><td><code>#NP(selector)</code></td><td>If code segment, interrupt-, trap-, or task gate, or TSS is not present.</td></tr>
<tr><td><code>#TS(selector)</code></td><td>If the RPL of the stack segment selector in the TSS is not equal to the DPL of the code segment being accessed by the interrupt or trap gate. If DPL of the stack segment descriptor pointed to by the stack segment selector in the TSS is not equal to the DPL of the code segment descriptor for the interrupt or trap gate. If the stack segment selector in the TSS is null. If the stack segment for the TSS is not a writable data segment. If segment-selector index for stack segment is outside descriptor table limits.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the interrupt vector number is outside the IDT limits.</td></tr>
<tr><td><code>#GP</code></td><td>If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit. If the interrupt vector number is outside the IDT limits.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
</div>
</body>
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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>INVD: Invalidate Internal Caches (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>INVD: Invalidate Internal Caches (x86 Instruction Set Reference)</title>
<h1>INVD</h1>
<h2>Invalidate Internal Caches</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>0F 08</code></td>
<td class="grid"><code>INVD</code></td>
<td class="grid">Flush internal caches; initiate flushing of external caches.</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Invalidates (flushes) the processor's internal caches and issues a special-function bus cycle that directs external caches to also flush themselves. Data held in internal caches is not written back to main memory.</p>
<p>After executing this instruction, the processor does not wait for the external caches to complete their flushing operation before proceeding with instruction execution. It is the responsibility of hardware to respond to the cache flush signal.</p>
<p>The INVD instruction is a privileged instruction. When the processor is running in protected mode, the CPL of a program or procedure must be 0 to execute this instruction.</p>
<p>Use this instruction with care. Data cached internally and not written back to main memory will be lost. Unless there is a specific requirement or benefit to flushing caches without writing back modified cache lines (for example, testing or fault recovery where cache coherency with main memory is not a concern), software should use the WBINVD instruction.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre>Flush<span class="operator">(</span>InternalCaches<span class="operator">)</span><span class="operator">;</span>
SignalFlush<span class="operator">(</span>ExternalCaches<span class="operator">)</span><span class="operator">;</span>
ContinueExecution<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>None.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>IA-32 Architecture Compatibility</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>The INVD instruction is implementation dependent; it may be implemented differently on different families of IA-32 processors. This instruction is not supported on IA-32 processors earlier than the Intel486 processor.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If the current privilege level is not 0.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
None.
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>The INVD instruction cannot be executed in virtual-8086 mode.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
</div>
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>INVLPG: Invalidate TLB Entry (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>INVLPG: Invalidate TLB Entry (x86 Instruction Set Reference)</title>
<h1>INVLPG</h1>
<h2>Invalidate TLB Entry</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>0F 01/7</code></td>
<td class="grid"><code>INVLPG m</code></td>
<td class="grid">Invalidate TLB Entry for page that contains m.</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Invalidates (flushes) the translation lookaside buffer (TLB) entry specified with the source operand. The source operand is a memory address. The processor determines the page that contains that address and flushes the TLB entry for that page.</p>
<p>The INVLPG instruction is a privileged instruction. When the processor is running in protected mode, the CPL of a program or procedure must be 0 to execute this instruction.</p>
<p>The INVLPG instruction normally flushes the TLB entry only for the specified page; however, in some cases, it flushes the entire TLB. See &quot;MOV-Move to/from Control Registers&quot; in this chapter for further information on operations that flush the TLB.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre>Flush<span class="operator">(</span>RelevantTLBEntries<span class="operator">)</span><span class="operator">;</span>
ContinueExecution<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span>
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>None.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>IA-32 Architecture Compatibility</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>The INVLPG instruction is implementation dependent, and its function may be implemented differently on different families of IA-32 processors. This instruction is not supported on IA-32 processors earlier than the Intel486 processor.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If the current privilege level is not 0.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If the current privilege level is not 0.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#UD</code></td><td>Operand is a register.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>The INVLPG instruction cannot be executed at the virtual-8086 mode.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
</div>
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>IRET/IRETD: Interrupt Return (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>IRET/IRETD: Interrupt Return (x86 Instruction Set Reference)</title>
<h1>IRET/IRETD</h1>
<h2>Interrupt Return</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>CF</code></td>
<td class="grid"><code>IRET</code></td>
<td class="grid">Interrupt return (16-bit operand size).</td>
</tr>
<tr>
<td class="grid"><code>CF</code></td>
<td class="grid"><code>IRETD</code></td>
<td class="grid">Interrupt return (32-bit operand size).</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Description</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>Returns program control from an exception or interrupt handler to a program or procedure that was interrupted by an exception, an external interrupt, or a software-generated interrupt. These instructions are also used to perform a return from a nested task. (A nested task is created when a CALL instruction is used to initiate a task switch or when an interrupt or exception causes a task switch to an interrupt or exception handler.) See the section titled &quot;Task Linking&quot; in Chapter 6 of the IA-32 Intel Architecture Software Developer's Manual, Volume 3.</p>
<p>IRET and IRETD are mnemonics for the same opcode. The IRETD mnemonic (interrupt return double) is intended for use when returning from an interrupt when using the 32-bit operand size; however, most assemblers use the IRET mnemonic interchangeably for both operand sizes.</p>
<p>In Real-Address Mode, the IRET instruction preforms a far return to the interrupted program or procedure. During this operation, the processor pops the return instruction pointer, return code segment selector, and EFLAGS image from the stack to the EIP, CS, and EFLAGS registers, respectively, and then resumes execution of the interrupted program or procedure.</p>
<p>In Protected Mode, the action of the IRET instruction depends on the settings of the NT (nested task) and VM flags in the EFLAGS register and the VM flag in the EFLAGS image stored on the current stack. Depending on the setting of these flags, the processor performs the following types of interrupt returns:</p>
<ul>
<li>Return from virtual-8086 mode.</li>
<li>Return to virtual-8086 mode.</li>
<li>Intra-privilege level return.</li>
<li>Inter-privilege level return.</li>
<li>Return from nested task (task switch).</li>
</ul>
<p>If the NT flag (EFLAGS register) is cleared, the IRET instruction performs a far return from the interrupt procedure, without a task switch. The code segment being returned to must be equally or less privileged than the interrupt handler routine (as indicated by the RPL field of the code segment selector popped from the stack). As with a real-address mode interrupt return, the IRET instruction pops the return instruction pointer, return code segment selector, and EFLAGS image from the stack to the EIP, CS, and EFLAGS registers, respectively, and then resumes execution of the interrupted program or procedure. If the return is to another privilege level, the IRET instruction also pops the stack pointer and SS from the stack, before resuming program execution. If the return is to virtual-8086 mode, the processor also pops the data segment registers from the stack.</p>
<p>If the NT flag is set, the IRET instruction performs a task switch (return) from a nested task (a task called with a CALL instruction, an interrupt, or an exception) back to the calling or inter- rupted task. The updated state of the task executing the IRET instruction is saved in its TSS. If the task is re-entered later, the code that follows the IRET instruction is executed.</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Operation</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<pre><span class="keyword">if</span><span class="operator">(</span>PE <span class="operator">==</span> <span class="number">0</span><span class="operator">)</span> {
	<span class="comment">//Real-Address-Mode</span>
	<span class="keyword">if</span><span class="operator">(</span>OperandSize <span class="operator">==</span> <span class="number">32</span><span class="operator">)</span> {
		<span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IsWithinStackLimits<span class="operator">(</span>TopStackBytes<span class="operator">(</span><span class="number">12</span><span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>SS<span class="operator">)</span><span class="operator">;</span> <span class="comment">//top 12 bytes of stack not within stack limits</span>
		<span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IsWithinCodeSegmentLimits<span class="operator">(</span>InstructionPointer<span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>GP<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
		EIP <span class="operator">=</span> Pop<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span>
		CS <span class="operator">=</span> Pop<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span> <span class="comment">//32-bit pop, high-order 16 bits discarded</span>
		TemporaryEFLAGS <span class="operator">=</span> Pop<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span>
		EFLAGS <span class="operator">=</span> <span class="operator">(</span>TemporaryEFLAGS <span class="operator">&amp;</span> <span class="number">0x257FD5</span><span class="operator">)</span> <span class="operator">|</span> <span class="operator">(</span>EFLAGS <span class="operator">&amp;</span> <span class="number">0x1A0000</span><span class="operator">)</span><span class="operator">;</span>
	}
	<span class="keyword">else</span> { <span class="comment">//OperandSize is 16</span>
		<span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IsWithinStackLimits<span class="operator">(</span>TopStackBytes<span class="operator">(</span><span class="number">6</span><span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>SS<span class="operator">)</span><span class="operator">;</span> <span class="comment">//top 6 bytes of stack not within stack limits</span>
		<span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IsWithinCodeSegmentLimits<span class="operator">(</span>InstructionPointer<span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>GP<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
		EIP <span class="operator">=</span> Pop<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span>
		EIP <span class="operator">=</span> EIP <span class="operator">&amp;</span> <span class="number">0xFFFF</span><span class="operator">;</span>
		CS <span class="operator">=</span> Pop<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span> <span class="comment">//16-bit pop</span>
		EFLAGS<span class="operator">[</span><span class="number">0..15</span><span class="operator">]</span> <span class="operator">=</span> Pop<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span>
	}
	<span class="comment">//END</span>
}
<span class="keyword">else</span> {
	<span class="comment">//Protected Mode</span>
	<span class="keyword">if</span><span class="operator">(</span>VM <span class="operator">==</span> <span class="number">1</span><span class="operator">)</span> {
		<span class="comment">//Virtual-8086 mode: PE == 1, VM == 1</span>
		<span class="comment">//Processor is in virtual-8086 mode when IRET is executed and stays in virtual-8086 mode</span>
		<span class="keyword">if</span><span class="operator">(</span>IOPL <span class="operator">==</span> <span class="number">3</span><span class="operator">)</span> { <span class="comment">//Virtual mode: PE=1, VM=1, IOPL=3</span>
			<span class="keyword">if</span><span class="operator">(</span>OperandSize <span class="operator">==</span> <span class="number">32</span><span class="operator">)</span> {
				<span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IsWithinStackLimits<span class="operator">(</span>TopStackBytes<span class="operator">(</span><span class="number">12</span><span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>SS<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span> <span class="comment">//top 12 bytes of stack not within stack limits</span>
				<span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IsWithinCodeSegmentLimits<span class="operator">(</span>InstructionPointer<span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>GP<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
				EIP <span class="operator">=</span> Pop<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span>
				CS <span class="operator">=</span> Pop<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span> <span class="comment">//32-bit pop, high-order 16 bits discarded</span>
				EFLAGS <span class="operator">=</span> Pop<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span>
				<span class="comment">//VM, IOPL, VIP and VIF EFLAGS bits are not modified by pop</span>
			}
			<span class="keyword">else</span> { <span class="comment">//OperandSize is 16</span>
				<span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IsWithinStackLimits<span class="operator">(</span>TopStackBytes<span class="operator">(</span><span class="number">6</span><span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>SS<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span> <span class="comment">//top 6 bytes of stack not within stack limits</span>
				<span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IsWithinCodeSegmentLimits<span class="operator">(</span>InstructionPointer<span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>GP<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
				EIP <span class="operator">=</span> Pop<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span>
				EIP <span class="operator">=</span> EIP <span class="operator">&amp;</span> <span class="number">0xFFFF</span><span class="operator">;</span>
				CS <span class="operator">=</span> Pop<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span> <span class="comment">//16-bit pop</span>
				EFLAGS<span class="operator">[</span><span class="number">0..15</span><span class="operator">]</span> <span class="operator">=</span> Pop<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span>
				<span class="comment">//VM, IOPL, VIP and VIF EFLAGS bits are not modified by pop</span>
			}
		}
		<span class="keyword">else</span> Exception<span class="operator">(</span>GP<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span> <span class="comment">//trap to virtual-8086 monitor: PE == 1, VM == 1, IOPL < 3</span>
		<span class="comment">//END</span>
	}
	<span class="keyword">if</span><span class="operator">(</span>NT <span class="operator">==</span> <span class="number">1</span><span class="operator">)</span> {
		<span class="comment">//Task return</span>
		<span class="comment">//PE == 1, VM == 0, NT == 1</span>
		SegmentSelector <span class="operator">=</span> ReadSegmentSelector<span class="operator">(</span>CurrentTSS<span class="operator">.</span>LinkField<span class="operator">)</span><span class="operator">;</span> <span class="comment">//Read segment selector in link field of current TSS</span>
		<span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IsGlobal<span class="operator">(</span><span class="operator">)</span> <span class="comment">/*local/global bit is set to local*/</span> <span class="operator">||</span> <span class="operator">!</span>IsWithinGDTLimits<span class="operator">(</span>Index<span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>TS<span class="operator">(</span>TSSSelector<span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
		TSSDescriptor <span class="operator">=</span> AccessTSS<span class="operator">(</span>CurrentTSS<span class="operator">.</span>LinkField<span class="operator">.</span>Task<span class="operator">)</span><span class="operator">;</span> <span class="comment">//Access TSS for task specified in link field of current TSS</span>
		<span class="keyword">if</span><span class="operator">(</span>TSSDescriptor<span class="operator">.</span>Type <span class="operator">!=</span> TSS <span class="operator">||</span> <span class="operator">!</span>IsBusy<span class="operator">(</span>TSS<span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>TS<span class="operator">(</span>TSSSelector<span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
		<span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IsPresent<span class="operator">(</span>TSS<span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>NP<span class="operator">(</span>TSSSelector<span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
		SwitchTasks<span class="operator">(</span>CurrenTSS<span class="operator">.</span>LinkField<span class="operator">.</span>TSS<span class="operator">,</span> WithoutNesting<span class="operator">)</span><span class="operator">;</span> <span class="comment">//Switch tasks (without nesting) to TSS specified in link field of current TSS</span>
		SetBusyState<span class="operator">(</span>AbandonedTask<span class="operator">,</span> NotBusy<span class="operator">)</span><span class="operator">;</span> <span class="comment">//Mark the task just abandoned as NOT BUSY</span>
		<span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IsWithinCodeSegmentLimit<span class="operator">(</span>EIP<span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>GP<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
		<span class="comment">//END</span>
	}
	<span class="keyword">if</span><span class="operator">(</span>OperandSize <span class="operator">==</span> <span class="number">32</span><span class="operator">)</span> {
		<span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IsWithinStackLimits<span class="operator">(</span>TopStackBytes<span class="operator">(</span><span class="number">12</span><span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>SS<span class="operator">)</span><span class="operator">;</span> <span class="comment">//top 12 bytes of stack not within stack limits</span>
		TemporaryEIP <span class="operator">=</span> Pop<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span>
		TemporaryCS <span class="operator">=</span> Pop<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span>
		TemporaryEFLAGS <span class="operator">=</span> Pop<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span>
	}
	<span class="keyword">else</span> { <span class="comment">//OperandSize == 16</span>
		<span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IsWithinStackLimits<span class="operator">(</span>TopStackBytes<span class="operator">(</span><span class="number">6</span><span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>SS<span class="operator">)</span><span class="operator">;</span> <span class="comment">//top 6 bytes of stack not within stack limits</span>
		TemporaryEIP <span class="operator">=</span> Pop<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span>
		TemporaryCS <span class="operator">=</span> Pop<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span>
		TemporaryEFLAGS <span class="operator">=</span> Pop<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span>
		TemporaryEIP <span class="operator">=</span> TemporaryEIP <span class="operator">&amp;</span> <span class="number">0xFFFF</span><span class="operator">;</span>
		TemporaryEFLAGS <span class="operator">=</span> TemporaryEFLAGS <span class="operator">&amp;</span> <span class="number">0xFFFF</span><span class="operator">;</span>
	}
	<span class="keyword">if</span><span class="operator">(</span>TemporaryEFLAGS<span class="operator">.</span>VM <span class="operator">==</span> <span class="number">1</span> <span class="operator">&amp;&amp;</span> CPL <span class="operator">==</span> <span class="number">0</span><span class="operator">)</span> {
		<span class="comment">//Interrupted procedure was in virtual-8086 mode: PE == 1, VM == 1 in flags image</span>
		<span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IsWithinStackLimits<span class="operator">(</span>TopStackBytes<span class="operator">(</span><span class="number">24</span><span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>SS<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span> <span class="comment">//top 24 bytes of stack not within stack limits</span>
		<span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IsWithinCodeSegmentLimits<span class="operator">(</span>InstructionPointer<span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>GP<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
		CS <span class="operator">=</span> TemporaryCS<span class="operator">;</span>
		EIP <span class="operator">=</span> TemporaryEIP<span class="operator">;</span>
		EFLAGS <span class="operator">=</span> TemporaryEFLAGS<span class="operator">;</span>
		TemporaryESP <span class="operator">=</span> Pop<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span>
		TemporarySS <span class="operator">=</span> Pop<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span>
		ES <span class="operator">=</span> Pop<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span> <span class="comment">//pop 2 words; throw away high-order word</span>
		DS <span class="operator">=</span> Pop<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span> <span class="comment">//pop 2 words; throw away high-order word</span>
		FS <span class="operator">=</span> Pop<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span> <span class="comment">//pop 2 words; throw away high-order word</span>
		GS <span class="operator">=</span> Pop<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span> <span class="comment">//pop 2 words; throw away high-order word</span>
		SS<span class="operator">:</span>ESP <span class="operator">=</span> TemporarySS<span class="operator">:</span>TemporaryESP<span class="operator">;</span>
		CPL <span class="operator">=</span> <span class="number">3</span><span class="operator">;</span>
		ResumeExecution<span class="operator">(</span><span class="operator">)</span> <span class="comment">//Resume execution in Virtual-8086 mode</span>
	}
	<span class="keyword">else</span> {
		<span class="comment">//Protected mode return</span>
		<span class="comment">//PE == 1, VM == 0 in flags image</span>
		<span class="keyword">if</span><span class="operator">(</span>ReturnCode<span class="operator">.</span>SegmentSelector <span class="operator">==</span> <span class="number">0</span><span class="operator">)</span> Exception<span class="operator">(</span>GP<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
		<span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IsWithinDescriptorTableLimits<span class="operator">(</span>ReturnCode<span class="operator">.</span>SegmentSelector<span class="operator">.</span>AddressesDescriptor<span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>GP<span class="operator">(</span>Selector<span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
		ReturnCode<span class="operator">.</span>SegmentDescriptor <span class="operator">=</span> ReadSegmentDescriptor<span class="operator">(</span>ReturnCode<span class="operator">.</span>SegmentSelector<span class="operator">)</span><span class="operator">;</span>
		<span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IsCodeSegment<span class="operator">(</span>ReturnCode<span class="operator">.</span>SegmentDescriptor<span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>GP<span class="operator">(</span>Selector<span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
		<span class="keyword">if</span><span class="operator">(</span>ReturnCode<span class="operator">.</span>SegmentSelector<span class="operator">.</span>RPL <span class="operator">&lt;</span> CPL<span class="operator">)</span> Exception<span class="operator">(</span>GP<span class="operator">(</span>Selector<span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
		<span class="keyword">if</span><span class="operator">(</span>IsConforming<span class="operator">(</span>ReturnCode<span class="operator">.</span>SegmentDescriptor<span class="operator">)</span> <span class="operator">&amp;&amp;</span> ReturnCode<span class="operator">.</span>Segment<span class="operator">.</span>DPL <span class="operator">&gt;</span> ReturnCode<span class="operator">.</span>SegmentSelector<span class="operator">.</span>RPL<span class="operator">)</span> Exception<span class="operator">(</span>GP<span class="operator">(</span>Selector<span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
		<span class="keyword">if</span><span class="operator">(</span>ReturnCode<span class="operator">.</span>SegmentSelector<span class="operator">.</span>RPL <span class="operator">&gt;</span> CPL<span class="operator">)</span> {
			<span class="comment">//Return to outer privilege level</span>
			<span class="keyword">if</span><span class="operator">(</span>OperandSize <span class="operator">==</span> <span class="number">32</span> <span class="operator">&amp;&amp;</span> <span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IsWithinStackLimits<span class="operator">(</span>TopStackBytes<span class="operator">(</span><span class="number">8</span><span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>SS<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span> <span class="comment">//top 8 bytes of stack not within stack limits</span>
			<span class="keyword">else</span> <span class="comment">/*OperandSize == 16*/</span> <span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IsWithinStackLimits<span class="operator">(</span>TopStackBytes<span class="operator">(</span><span class="number">4</span><span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>SS<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span> <span class="comment">//top 4 bytes of stack not within stack limits</span>
			StackSegmentSelector <span class="operator">=</span> ReadReturnSegmentSelector<span class="operator">(</span><span class="operator">)</span><span class="operator">;</span>
			<span class="keyword">if</span><span class="operator">(</span>StackSegmentSelector <span class="operator">==</span> <span class="number">0</span><span class="operator">)</span> Exception<span class="operator">(</span>GP<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
			<span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IsWithinDescriptorTableLimits<span class="operator">(</span>ReturnStackSegmentSelector<span class="operator">.</span>Index<span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>GP<span class="operator">(</span>SSSelector<span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
			SegmentDescriptor <span class="operator">=</span> ReadSegmenDescriptor<span class="operator">(</span>ReturnSegmentSelector<span class="operator">)</span><span class="operator">;</span>
			<span class="keyword">if</span><span class="operator">(</span>StackSegmentSelector<span class="operator">.</span>RPL <span class="operator">!=</span> ReturnCode<span class="operator">.</span>SegmentSelector<span class="operator">.</span>RPL<span class="operator">)</span> {
				<span class="keyword">if</span><span class="operator">(</span>StackSegmentSelector<span class="operator">.</span>RPL <span class="operator">!=</span> ReturnCode<span class="operator">.</span>SegmentSelector<span class="operator">.</span>RPL <span class="operator">||</span> <span class="operator">!</span>IndicatesWritableDataSegment<span class="operator">(</span>StackSegmentDescriptor<span class="operator">)</span> <span class="operator">||</span> StackSegment<span class="operator">.</span>DPL <span class="operator">!=</span> ReturnCode<span class="operator">.</span>SegmentSelector<span class="operator">.</span>RPL<span class="operator">)</span> Exception<span class="operator">(</span>GP<span class="operator">(</span>SSSelector<span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
				<span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IsPresent<span class="operator">(</span>StackSegment<span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>SS<span class="operator">(</span>SSSelector<span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
			}
			<span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IsWithinCodeSegmentLimit<span class="operator">(</span>TemporaryEIP<span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>GP<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
			EIP <span class="operator">=</span> TemporaryIP<span class="operator">;</span>
			CS <span class="operator">=</span> TemporaryCS<span class="operator">;</span>
			EFLAGS<span class="operator">.</span>CF <span class="operator">=</span> TemporaryEFLAGS<span class="operator">.</span>CF<span class="operator">;</span>
			EFLAGS<span class="operator">.</span>PF <span class="operator">=</span> TemporaryEFLAGS<span class="operator">.</span>PF<span class="operator">;</span>
			EFLAGS<span class="operator">.</span>AF <span class="operator">=</span> TemporaryEFLAGS<span class="operator">.</span>ZF<span class="operator">;</span>
			EFLAGS<span class="operator">.</span>SF <span class="operator">=</span> TemporaryEFLAGS<span class="operator">.</span>SF<span class="operator">;</span>
			EFLAGS<span class="operator">.</span>TF <span class="operator">=</span> TemporaryEFLAGS<span class="operator">.</span>DF<span class="operator">;</span>
			EFLAGS<span class="operator">.</span>OF <span class="operator">=</span> TemporaryEFLAGS<span class="operator">.</span>OF<span class="operator">;</span>
			EFLAGS<span class="operator">.</span>NT <span class="operator">=</span> TemporaryEFLAGS<span class="operator">.</span>NT<span class="operator">;</span>
			<span class="keyword">if</span><span class="operator">(</span>OperandSize <span class="operator">==</span> <span class="number">32</span><span class="operator">)</span> {
				EFLAGS<span class="operator">.</span>RF <span class="operator">=</span> TemporaryEFLAGS<span class="operator">.</span>RF<span class="operator">;</span>
				EFLAGS<span class="operator">.</span>AC <span class="operator">=</span> TemporaryEFLAGS<span class="operator">.</span>AC<span class="operator">;</span>
				EFLAGS<span class="operator">.</span>ID <span class="operator">=</span> TemporaryEFLAGS<span class="operator">.</span>ID<span class="operator">;</span>
			}
			<span class="keyword">if</span><span class="operator">(</span>CPL <span class="operator">&lt;=</span> IOPL<span class="operator">)</span> EFLAGS<span class="operator">.</span>IF <span class="operator">=</span> TemporaryEFLAGS<span class="operator">.</span>IF<span class="operator">;</span>
			<span class="keyword">if</span><span class="operator">(</span>CPL <span class="operator">==</span> <span class="number">0</span><span class="operator">)</span> {
				EFLAGS<span class="operator">.</span>IOPL <span class="operator">=</span> TemporaryEFLAGS<span class="operator">.</span>IOPL<span class="operator">;</span>
				<span class="keyword">if</span><span class="operator">(</span>OperandSize <span class="operator">==</span> <span class="number">32</span><span class="operator">)</span> {
					EFLAGS<span class="operator">.</span>VM <span class="operator">=</span> TemporaryEFLAGS<span class="operator">.</span>VM<span class="operator">;</span>
					EFLAGS<span class="operator">.</span>VIF <span class="operator">=</span> TemporaryEFLAGS<span class="operator">.</span>VIF<span class="operator">;</span>
					EFLAGS<span class="operator">.</span>VIP <span class="operator">=</span> TemporaryEFLAGS<span class="operator">.</span>VIP<span class="operator">;</span>
				}
			}
			<span class="comment">//perform operation for each of the segment registers</span>
			SegmentRegisters<span class="operator">[</span><span class="operator">]</span> <span class="operator">=</span> {ES<span class="operator">,</span> FS<span class="operator">,</span> GS<span class="operator">,</span> DS}<span class="operator">;</span>
			<span class="keyword">while</span><span class="operator">(</span>SegmentRegister <span class="operator">=</span> SegmentRegisters<span class="operator">.</span>Next<span class="operator">(</span><span class="operator">)</span><span class="operator">)</span> <span class="keyword">if</span><span class="operator">(</span><span class="operator">(</span>PointsToDate<span class="operator">(</span>SegmentRegister<span class="operator">)</span> <span class="operator">||</span> <span class="operator">!</span>IsConformingCodeSegment<span class="operator">(</span>SegmentRegister<span class="operator">)</span><span class="operator">)</span> <span class="operator">&amp;&amp;</span> CPL <span class="operator">&gt;</span> SegmentDescriptor<span class="operator">.</span>DPL <span class="comment">/*stored in hidden part of segment register*/</span><span class="operator">)</span> SegmentSelector <span class="operator">=</span> <span class="number">0</span><span class="operator">;</span> <span class="comment">//segment register invalid; null segment selector</span>
			<span class="comment">//END</span>
		}
		<span class="keyword">else</span> {
			<span class="comment">//Same privilege level</span>
			<span class="comment">//PE=1, VM=0 in flags image, RPL=CPL</span>
			<span class="keyword">if</span><span class="operator">(</span><span class="operator">!</span>IsWithinCodeSegmentLimits<span class="operator">(</span>EIP<span class="operator">)</span><span class="operator">)</span> Exception<span class="operator">(</span>GP<span class="operator">(</span><span class="number">0</span><span class="operator">)</span><span class="operator">)</span><span class="operator">;</span>
			EIP <span class="operator">=</span> TemporaryEIP<span class="operator">;</span>
			CS <span class="operator">=</span> TemporaryCS<span class="operator">;</span> <span class="comment">//segment descriptor information also loaded</span>
			EFLAGS<span class="operator">.</span>CF <span class="operator">=</span> TemporaryEFLAGS<span class="operator">.</span>CF<span class="operator">;</span>
			EFLAGS<span class="operator">.</span>PF <span class="operator">=</span> TemporaryEFLAGS<span class="operator">.</span>PF<span class="operator">;</span>
			EFLAGS<span class="operator">.</span>AF <span class="operator">=</span> TemporaryEFLAGS<span class="operator">.</span>ZF<span class="operator">;</span>
			EFLAGS<span class="operator">.</span>SF <span class="operator">=</span> TemporaryEFLAGS<span class="operator">.</span>SF<span class="operator">;</span>
			EFLAGS<span class="operator">.</span>TF <span class="operator">=</span> TemporaryEFLAGS<span class="operator">.</span>DF<span class="operator">;</span>
			EFLAGS<span class="operator">.</span>OF <span class="operator">=</span> TemporaryEFLAGS<span class="operator">.</span>OF<span class="operator">;</span>
			EFLAGS<span class="operator">.</span>NT <span class="operator">=</span> TemporaryEFLAGS<span class="operator">.</span>NT<span class="operator">;</span>
			<span class="keyword">if</span><span class="operator">(</span>OperandSize <span class="operator">==</span> <span class="number">32</span><span class="operator">)</span> {
				EFLAGS<span class="operator">.</span>RF <span class="operator">=</span> TemporaryEFLAGS<span class="operator">.</span>RF<span class="operator">;</span>
				EFLAGS<span class="operator">.</span>AC <span class="operator">=</span> TemporaryEFLAGS<span class="operator">.</span>AC<span class="operator">;</span>
				EFLAGS<span class="operator">.</span>ID <span class="operator">=</span> TemporaryEFLAGS<span class="operator">.</span>ID<span class="operator">;</span>
			}
			<span class="keyword">if</span><span class="operator">(</span>CPL <span class="operator">&lt;=</span> IOPL<span class="operator">)</span> EFLAGS<span class="operator">.</span>IF <span class="operator">=</span> TemporaryEFLAGS<span class="operator">.</span>IF<span class="operator">;</span>
			<span class="keyword">if</span><span class="operator">(</span>CPL <span class="operator">==</span> <span class="number">0</span><span class="operator">)</span> {
				EFLAGS<span class="operator">.</span>IOPL <span class="operator">=</span> TemporaryEFLAGS<span class="operator">.</span>IOPL<span class="operator">;</span>
				<span class="keyword">if</span><span class="operator">(</span>OperandSize <span class="operator">==</span> <span class="number">32</span><span class="operator">)</span> {
					EFLAGS<span class="operator">.</span>VM <span class="operator">=</span> TemporaryEFLAGS<span class="operator">.</span>VM<span class="operator">;</span>
					EFLAGS<span class="operator">.</span>VIF <span class="operator">=</span> TemporaryEFLAGS<span class="operator">.</span>VIF<span class="operator">;</span>
					EFLAGS<span class="operator">.</span>VIP <span class="operator">=</span> TemporaryEFLAGS<span class="operator">.</span>VIP<span class="operator">;</span>
				}
			}
			<span class="comment">//END</span>
		}
	}
}
</pre>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Flags affected</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<p>All the flags and fields in the EFLAGS register are potentially modified, depending on the mode of operation of the processor. If performing a return from a nested task to a previous task, the EFLAGS register will be modified according to the EFLAGS image stored in the previous task's TSS.
</p>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Protected Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If the return code or stack segment selector is null. If the return instruction pointer is not within the return code segment limit.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If the return code or stack segment selector is null. If the return instruction pointer is not within the return code segment limit.</td></tr>
<tr><td><code>#GP(selector)</code></td><td>If a segment selector index is outside its descriptor table limits. If the return code segment selector RPL is greater than the CPL. If the DPL of a conforming-code segment is greater than the return code segment selector RPL. If the DPL for a nonconforming-code segment is not equal to the RPL of the code segment selector. If the stack segment descriptor DPL is not equal to the RPL of the return code segment selector. If the stack segment is not a writable data segment. If the stack segment selector RPL is not equal to the RPL of the return code segment selector. If the segment descriptor for a code segment does not indicate it is a code segment. If the segment selector for a TSS has its local/global bit set for local. If a TSS segment descriptor specifies that the TSS is not busy. If a TSS segment descriptor specifies that the TSS is not available.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If the top bytes of stack are not within stack limits.</td></tr>
<tr><td><code>#NP(selector)</code></td><td>If the return code or stack segment is not present.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Real-Address Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP</code></td><td>If the return instruction pointer is not within the return code segment limit.</td></tr>
<tr><td><code>#GP</code></td><td>If the return instruction pointer is not within the return code segment limit.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
<object>
<table class="box">
<tr>
<th>Virtual-8086 Mode Exceptions</th>
</tr>
<tr>
<td class="instruction_set_reference_box">
<div>
<table class="operations_table">
<tr><td><code>#GP(0)</code></td><td>If the return instruction pointer is not within the return code segment limit. IF IOPL not equal to 3.</td></tr>
<tr><td><code>#GP(0)</code></td><td>If the return instruction pointer is not within the return code segment limit. IF IOPL not equal to 3.</td></tr>
<tr><td><code>#PF(fault-code)</code></td><td>If a page fault occurs.</td></tr>
<tr><td><code>#SS(0)</code></td><td>If the top bytes of stack are not within stack limits.</td></tr>
</table>
</div>
</td>
</tr>
</table>
</object>
</div>
</body>
</html>

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML Basic 1.1//EN" "http://www.w3.org/TR/xhtml-basic/xhtml-basic11.dtd">
<html>
<head>
<link rel="stylesheet" type="text/css" href="../style/style.css" />
<title>Jcc: Jump if Condition Is Met (x86 Instruction Set Reference)</title>
</head>
<body>
<div class="main_container"><h1>x86 Instruction Set Reference</h1>
<title>Jcc: Jump if Condition Is Met (x86 Instruction Set Reference)</title>
<h1>Jcc</h1>
<h2>Jump if Condition Is Met</h2>
<object>
<table class="box">
<tr>
<th>Opcode</th>
<th>Mnemonic</th>
<th>Description</th>
</tr>
<tr>
<td class="grid"><code>77 cb</code></td>
<td class="grid"><code>JA rel8</code></td>
<td class="grid">Jump short if above (CF=0 and ZF=0).</td>
</tr>
<tr>
<td class="grid"><code>73 cb</code></td>
<td class="grid"><code>JAE rel8</code></td>
<td class="grid">Jump short if above or equal (CF=0).</td>
</tr>
<tr>
<td class="grid"><code>72 cb</code></td>
<td class="grid"><code>JB rel8</code></td>
<td class="grid">Jump short if below (CF=1).</td>
</tr>
<tr>
<td class="grid"><code>76 cb</code></td>
<td class="grid"><code>JBE rel8</code></td>
<td class="grid">Jump short if below or equal (CF=1 or ZF=1).</td>
</tr>
<tr>
<td class="grid"><code>72 cb</code></td>
<td class="grid"><code>JC rel8</code></td>
<td class="grid">Jump short if carry (CF=1).</td>
</tr>
<tr>
<td class="grid"><code>E3 cb</code></td>
<td class="grid"><code>JCXZ rel8</code></td>
<td class="grid">Jump short if CX register is 0.</td>
</tr>
<tr>
<td class="grid"><code>E3 cb</code></td>
<td class="grid"><code>JECXZ rel8</code></td>
<td class="grid">Jump short if ECX register is 0.</td>
</tr>
<tr>
<td class="grid"><code>74 cb</code></td>
<td class="grid"><code>JE rel8</code></td>
<td class="grid">Jump short if equal (ZF=1).</td>
</tr>
<tr>
<td class="grid"><code>7F cb</code></td>
<td class="grid"><code>JG rel8</code></td>
<td class="grid">Jump short if greater (ZF=0 and SF=OF).</td>
</tr>
<tr>
<td class="grid"><code>7D cb</code></td>
<td class="grid"><code>JGE rel8</code></td>
<td class="grid">Jump short if greater or equal (SF=OF).</td>
</tr>
<tr>
<td class="grid"><code>7C cb</code></td>
<td class="grid"><code>JL rel8</code></td>
<td class="grid">Jump short if less (SF&lt;&gt;OF).</td>
</tr>
<tr>
<td class="grid"><code>7E cb</code></td>
<td class="grid"><code>JLE rel8</code></td>
<td class="grid">Jump short if less or equal (ZF=1 or SF&lt;&gt;OF).</td>
</tr>
<tr>
<td class="grid"><code>76 cb</code></td>
<td class="grid"><code>JNA rel8</code></td>
<td class="grid">Jump short if not above (CF=1 or ZF=1).</td>
</tr>
<tr>
<td class="grid"><code>72 cb</code></td>
<td class="grid"><code>JNAE rel8</code></td>
<td class="grid">Jump short if not above or equal (CF=1).</td>
</tr>
<tr>
<td class="grid"><code>73 cb</code></td>
<td class="grid"><code>JNB rel8</code></td>
<td class="grid">Jump short if not below (CF=0).</td>
</tr>
<tr>
<td class="grid"><code>77 cb</code></td>
<td class="grid"><code>JNBE rel8</code></td>
<td class="grid">Jump short if not below or equal (CF=0 and ZF=0).</td>
</tr>
<tr>
<td class="grid"><code>73 cb</code></td>
<td class="grid"><code>JNC rel8</code></td>
<td class="grid">Jump short if not carry (CF=0).</td>
</tr>
<tr>
<td class="grid"><code>75 cb</code></td>
<td class="grid"><code>JNE rel8</code></td>
<td class="grid">Jump short if not equal (ZF=0).</td>
</tr>
<tr>
<td class="grid"><code>7E cb</code></td>
<td class="grid"><code>JNG rel8</code></td>
<td class="grid">Jump short if not greater (ZF=1 or SF&lt;&gt;OF).</td>
</tr>
<tr>
<td class="grid"><code>7C cb</code></td>
<td class="grid"><code>JNGE rel8</code></td>
<td class="grid">Jump short if not greater or equal (SF&lt;&gt;OF).</td>
</tr>
<tr>
<td class="grid"><code>7D cb</code></td>
<td class="grid"><code>JNL rel8</code></td>
<td class="grid">Jump short if not less (SF=OF).</td>
</tr>
<tr>
<td class="grid"><code>7F cb</code></td>
<td class="grid"><code>JNLE rel8</code></td>
<td class="grid">Jump short if not less or equal (ZF=0 and SF=OF).</td>
</tr>
<tr>
<td class="grid"><code>71 cb</code></td>
<td class="grid"><code>JNO rel8</code></td>
<td class="grid">Jump short if not overflow (OF=0).</td>
</tr>
<tr>
<td class="grid"><code>7B cb</code></td>
<td class="grid"><code>JNP rel8</code></td>
<td class="grid">Jump short if not parity (PF=0).</td>
</tr>
<tr>
<td class="grid"><code>79 cb</code></td>
<td class="grid"><code>JNS rel8</code></td>
<td class="grid">Jump short if not sign (SF=0).</td>
</tr>
<tr>
<td class="grid"><code>75 cb</code></td>
<td class="grid"><code>JNZ rel8</code></td>
<td class="grid">Jump short if not zero (ZF=0).</td>
</tr>
<tr>
<td class="grid"><code>70 cb</code></td>
<td class="grid"><code>JO rel8</code></td>
<td class="grid">Jump short if overflow (OF=1).</td>
</tr>
<tr>
<td class="grid"><code>7A cb</code></td>
<td class="grid"><code>JP rel8</code></td>
<td class="grid">Jump short if parity (PF=1).</td>
</tr>
<tr>
<td class="grid"><code>7A cb</code></td>
<td class="grid"><code>JPE rel8</code></td>
<td class="grid">Jump short if parity even (PF=1).</td>
</tr>
<tr>
<td class="grid"><code>7B cb</code></td>
<td class="grid"><code>JPO rel8</code></td>
<td class="grid">Jump short if parity odd (PF=0).</td>
</tr>
<tr>
<td class="grid"><code>78 cb</code></td>
<td class="grid"><code>JS rel8</code></td>
<td class="grid">Jump short if sign (SF=1).</td>
</tr>
<tr>
<td class="grid"><code>74 cb</code></td>
<td class="grid"><code>JZ rel8</code></td>
<td class="grid">Jump short if zero (ZF = 1).</td>
</tr>
<tr>
<td class="grid"><code>0F 87 cw/cd</code></td>
<td class="grid"><code>JA rel16/32</code></td>
<td class="grid">Jump near if above (CF=0 and ZF=0).</td>
</tr>
<tr>
<td class="grid"><code>0F 83 cw/cd</code></td>
<td class="grid"><code>JAE rel16/32</code></td>
<td class="grid">Jump near if above or equal (CF=0).</td>
</tr>
<tr>
<td class="grid"><code>0F 82 cw/cd</code></td>
<td class="grid"><code>JB rel16/32</code></td>
<td class="grid">Jump near if below (CF=1).</td>
</tr>
<tr>
<td class="grid"><code>0F 86 cw/cd</code></td>
<td class="grid"><code>JBE rel16/32</code></td>
<td class="grid">Jump near if below or equal (CF=1 or ZF=1).</td>
</tr>
<tr>
<td class="grid"><code>0F 82 cw/cd</code></td>
<td class="grid"><code>JC rel16/32</code></td>
<td class="grid">Jump near if carry (CF=1).</td>
</tr>
<tr>
<td class="grid"><code>0F 84 cw/cd</code></td>
<td class="grid"><code>JE rel16/32</code></td>
<td class="grid">Jump near if equal (ZF=1).</td>
</tr>
<tr>
<td class="grid"><code>0F 84 cw/cd</code></td>
<td class="grid"><code>JZ rel16/32</code></td>
<td class="grid">Jump near if 0 (ZF=1).</td>
</tr>
<tr>
<td class="grid"><code>0F 8F cw/cd</code></td>
<td class="grid"><code>JG rel16/32</code></td>
<td class="grid">Jump near if greater (ZF=0 and SF=OF).</td>
</tr>
<tr>
<td class="grid"><code>0F 8D cw/cd</code></td>
<td class="grid"><code>JGE rel16/32</code></td>
<td class="grid">Jump near if greater or equal (SF=OF).</td>
</tr>
<tr>
<td class="grid"><code>0F 8C cw/cd</code></td>
<td class="grid"><code>JL rel16/32</code></td>
<td class="grid">Jump near if less (SF&lt;&gt;OF).</td>
</tr>
<tr>
<td class="grid"><code>0F 8E cw/cd</code></td>
<td class="grid"><code>JLE rel16/32</code></td>
<td class="grid">Jump near if less or equal (ZF=1 or SF&lt;&gt;OF).</td>
</tr>
<tr>
<td class="grid"><code>0F 86 cw/cd</code></td>
<td class="grid"><code>JNA rel16/32</code></td>
<td class="grid">Jump near if not above (CF=1 or ZF=1).</td>
</tr>
<tr>
<td class="grid"><code>0F 82 cw/cd</code></td>
<td class="grid"><code>JNAE rel16/32</code></td>
<td class="grid">Jump near if not above or equal (CF=1).</td>
</tr>
<tr>
<td class="grid"><code>0F 83 cw/cd</code></td>
<td class="grid"><code>JNB rel16/32</code></td>
<td class="grid">Jump near if not below (CF=0).</td>
</tr>
<tr>
<td class="grid"><code>0F 87 cw/cd</code></td>
<td class="grid"><code>JNBE rel16/32</code></td>
<td class="grid">Jump near if not below or equal (CF=0 and ZF=0).</td>
</tr>
<tr>
<td class="grid"><code>0F 83 cw/cd</code></td>
<td class="grid"><code>JNC rel16/32</code></td>
<td class="grid">Jump near if not carry (CF=0).</td>
</tr>
<tr>
<td class="grid"><code>0F 85 cw/cd</code></td>
<td class="grid"><code>JNE rel16/32</code></td>
<td class="grid">Jump near if not equal (ZF=0).</td>
</tr>
<tr>
<td class="grid"><code>0F 8E cw/cd</code></td><