<h2>General Purpose Registers</h2>
<img align="right" valign="top"
The Mega-processor has four general purpose 16 bit registers: R0, R1, R2, R3.

There are 12 1-byte instructions to move data around from any general purpose register to any other.

R0 can also exchange data with the Stack Pointer (SP) -- instructions MOVE R0,SP and move SP,R0 --,<br>
and with the program counter -- instructions JMP (R0) and JSR (R0) --

R2 and R3 can also serve as index registers with optional automatic postincrement.

<h2>Program Counter</h2>
There is a 16 bit program counter, PC.

<h2>Stack Pointer</h2>
There is a 16 bit register dedicated as the stack pointer SP.

The PUSH instruction performs a predecrement save of a register (R0..R3, PS)<br>
The POP instruction performs a postincrement restore of a register.<br>
R0..R3 are saved/restored as 16 bit values, PS is saved/restored as 8 bits.<br>
There are also 2 specific MOVE instructions to move data from SP to R0, or vice-versa.

<h2>Processor Status Register</h2>
<p>There is a processor status register, PS. Whilst PS is internally a 16 bit register only 8 bit are visible to the user.<br>
The other hidden 8 bits are used during complex operations such as multiplication etc. and do not convey any information from one instruction to the next.
</p>
The user accessible status bits are:
<br>
<br>
<table class="wikiTable">
<tbody>
<tr>
  <td>0</td>

  <td>Enable interrupts. Set/cleared by user.<br>
      Also cleared on servicing an
</tr>
<tr>
  <td>1</td>

  <td>Set/cleared when result is
</tr>
<tr>
  <td>2</td><td>

  <td>Set/cleared when result is
</tr>
<tr>
  <td>3</td>

  <td>Set/cleared when there was/was not an overflow</td>
</tr>
<tr>
  <td>4</td>

  <td>Set/cleared when there was a carry<br>
      (not cleared on non-arithmetic operations so can be used for extended
      arithmetic)</td>
</tr>
<tr>
  <td>5</td>

  <td>Set/cleared when there was a carry</td>
</tr>
<tr>
  <td>6</td>

  <td>Controls division mode</td>
</tr>
<tr>
  <td>7</td>

  <td>User bit.<br>
      May be used for conditional branches,<br>
      the BUS and BUC instructions are provided for this.<br>
      Does not otherwise affect, and is not affected by processor operation<br>
      but must be set/cleared explicitly by user.</td>
</tr>
</tbody>
</table>