D 2015-07-30T16:11:24.848 L Programming\sModel P fea2c8054c960fa8ad696a63ecd4eb04f0967eab U jos W 2626
There is a processor status register, PS. Whilst PS is internally a 16 bit register only 8 bit are visible to the user.
The other hidden 8 bits are used during complex operations such as multiplication etc. and do not convey any information from one instruction to the next.
0 | I | Enable interrupts. Set/cleared by user. Also cleared on servicing an interrupt/exception. |
1 | N | Set/cleared when result is negative/positive |
2 | Z | Set/cleared when result is zero/non-zero |
3 | V | Set/cleared when there was/was not an overflow |
4 | X | Set/cleared when there was a carry (not cleared on non-arithmetic operations so can be used for extended arithmetic) |
5 | C | Set/cleared when there was a carry |
6 | D | Controls division mode |
7 | U | User bit. May be used for conditional branches, the BUS and BUC instructions are provided for this. Does not otherwise affect, and is not affected by processor operation but must be set/cleared explicitly by user. |