<h1>Register description</h1>
<table class="wikiTable">
<tbody>
<tr>
  <td>RA</td>
  <td>Destination. Any of registers R0, R1, R2, R3</td>
</tr>
<tr>
  <td>RB</td>
  <td>Source. Any of registers R0, R1, R2, R3 (possibly with exception of RA, see notes)</td>
</tr>
<tr>
  <td>RC</td>
  <td>Destination. May be either R0 or R1</td>
</tr>
<tr>
  <td>RI</td>
  <td>Index. May be either R2 or R3</td>
</tr>
<tr>
  <td>sz</td>
  <td>Size. May be B for byte or W for word</td>
</tr>
<tr>
  <td>wt</td>
  <td>Weight. Used to specify the calculation of a weight (count
    of ones) value.</td>
</tr>
</tbody>
</table>

<h1>Instruction set</h1>
<table class="wikiTable" >
<col width="210">
  <tbody>
    <tr>


    </tr>
    <tr>
      <td>ABS&nbsp;&nbsp;&nbsp;&nbsp; RA</td>
      <td><br>
      </td>
    </tr>
    <tr>
      <td>ADD&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RA,RB</td>
      <td>RB may equal RA</td>
    </tr>
    <tr>
      <td>ADDI &nbsp;&nbsp;&nbsp; SP, #data</td>
      <td>data is 8 bit signed value</td>
    </tr>
    <tr>
      <td>ADDQ&nbsp;&nbsp;&nbsp; RA, #small</td>
      <td>The small value may be 1, 2, -1, or -2. This instruction is encoded as a single byte.<br>
      </td>
    </tr>
    <tr>
      <td>ADDX&nbsp;&nbsp;&nbsp; R0, R1</td>
      <td><br>
      </td>
    </tr>
    <tr>
      <td>AND&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RA, RB</td>
      <td>RB may not equal RA</td>
    </tr>
    <tr>
      <td>ANDI&nbsp;&nbsp;&nbsp;&nbsp;PS, #data</td>
      <td>data is 8 bits</td>
    </tr>
    <tr>
      <td>ASL{.wt} RA, descriptor<br>
          ASR{.wt} RA, descriptor</td>
      <td>Arithmetic shift.<br>See notes on shift instructions below.</td>
    </tr>
    <tr>
      <td>Bcc&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;address</td>
      <td>Conditional branch. The target is stored as a signed 8 bit
        displacement, -128...127. There are 16 possibilities:<br>
            <table class="wikiTable">
            <tbody>
            <tr><td><b>BCC:</b> C C
            <tr><td><b>BNE:</b> Z clear (not Z set
            <tr><td><b>BVC:</b> V V
            <tr><td><b>BPL:</b> N clear N set

            <tr><td><b>BGT:</b> Use for 2s complement Use for 2s complement
            <tr><td><b>BUC:</b> U U
            <tr><td><b>BHI:</b> Branch Higher.<br>Similar to BGT but for unsigned Branch on Lower or Same.<br>Similar to BLE but for unsigned
            </tbody>
            </table>
      </td>
    </tr>
    <tr>
      <td>BCHG&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RA, descriptor</td>
      <td>Invert specified bit in destination register.<br>
        See notes on BIT instructions below</td>
    </tr>
    <tr>
      <td>BCLR&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RA, descriptor</td>
      <td>Clear specified bit in destination register.<br>
        See notes on BIT instructions below</td>
    </tr>
    <tr>
      <td>BSET&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RA, descriptor</td>
      <td>Set specified bit in destination register.<br>
        See notes on BIT instructions below</td>
    </tr>
    <tr>
      <td>BTST&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RA, descriptor</td>
      <td>Test specified bit in destination register.<br>
        See notes on BIT instructions below</td>
    </tr>
    <tr>
      <td>CLR&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RA</td>
      <td>Alias for XOR RA, RA</td>
    </tr>
    <tr>
      <td>CMP&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RA, RB</td>
      <td>RB may not equal RA</td>
    </tr>
    <tr>
      <td>DEC&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RA</td>
      <td>Alias for ADDQ RA, #-1</td>
    </tr>
    <tr>
      <td>DIVS<br>
          DIVU</td>
      <td>This calculates R0/R1.<br>
        R0 and R1 are left unchanged. R2 holds the quotient. R3
        holds the remainder.<br>
        There are two ways of defining signed division, both have
        validity. Both are implemented, controlled by the D bit of
        the PS register. The difference lies in whether or not
        negative remainders are allowed.<br>
        <table class="wikiTable">
          <tbody>
            <tr>
              <td><br>
              </td>
              <td>D = 0</td>
              <td>D = 1</td>
            </tr>
            <tr>

              <td>Q = 4, R = 1</td>
              <td>Q = 4, R = 1</td>
            </tr>
            <tr>

              <td>Q =
                -4, R = 1</td>
              <td>Q
                = -4, R = 1</td>
            </tr>
            <tr>

              <td>Q = -5, R = 2</td>
              <td>Q = -4, R = -1</td>
            </tr>
            <tr>

              <td>Q = 5, R = 2</td>
              <td>Q = 4, R = -1</td>
            </tr>
          </tbody>
        </table>
        <br>
        Divide by zero is trapped and causes vector #2 to be taken.<br>
      </td>
    </tr>
    <tr>
      <td>INC&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RA</td>
      <td>Alias for ADDQ RA, #1</td>
    </tr>
    <tr>
      <td>INV&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RA</td>
      <td>Invert all bits</td>
    </tr>
    <tr>
      <td>JMP&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;(R0)<br>
          JMP&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; address</td>
      <td>Jump to specified location.</td>
    </tr>
    <tr>
      <td>JSR&nbsp;&nbsp;&nbsp;&nbsp; (R0)<br>
          JSR&nbsp;&nbsp;&nbsp;&nbsp; address</td>
      <td>Jump to subroutine, pushes return address on stack</td>
    </tr>
    <tr>
      <td>LD.sz&nbsp;&nbsp;&nbsp; RA, address<br>
          LD.sz&nbsp;&nbsp;&nbsp; RC, (RI)<br>
          LD.sz&nbsp;&nbsp;&nbsp; RC, (RI++)<br>
          LD.sz&nbsp;&nbsp;&nbsp; RA, (SP + m)<br>
          LD.sz&nbsp;&nbsp;&nbsp; RA, #immediate</td>
      <td>Bytes are zero extended on loading to fill the 16 bit
        destination register.<br>
        The m value used for stack relative addressing is 8 bit
        unsigned.<br>
      </td>
    </tr>
    <tr>
      <td>LSL{.wt}&nbsp;&nbsp;RA, descriptor<br>
          LSR{.wt}&nbsp;&nbsp; RA, descriptor</td>
      <td>Logical shift.<br>
        See notes on shift instructions below.</td>
    </tr>
    <tr>
      <td>MOVE&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RA, RB<br>
          MOVE&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R0, SP<br>
          MOVE&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; SP, R0</td>
      <td>RB may not equal RA</td>
    </tr>
    <tr>
      <td>MULS<br>
          MULU</td>
      <td>This calculates R0*R1 to create a 32 bit result.<br>
        The least significant 16 bits of the result are stored in
        R2, the most significant 16 bits are stored in R3.<br>
        If it is a signed operation then R0 will hold the value of
        an internal calculation. If it is an unsigned operation R0
        will be unchanged.<br>
        R1 is always left unchanged.<br>
      </td>
    </tr>
    <tr>
      <td>NEG&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RA</td>
      <td><br>
      </td>
    </tr>
    <tr>
      <td>NEGX&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;R0</td>
      <td><br>
      </td>
    </tr>
    <tr>
      <td>NOP</td>
      <td><br>
      </td>
    </tr>
    <tr>
      <td>OR&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RA, RB</td>
      <td>RB may not equal RA</td>
    </tr>
    <tr>
      <td>ORI&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;PS, # data</td>
      <td>data is 8 bits</td>
    </tr>
    <tr>
      <td>POP&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;RA<br>
          POP &nbsp; &nbsp; &nbsp;&nbsp; PS</td>
      <td><br>
      </td>
    </tr>
    <tr>
      <td>PUSH
          &nbsp; &nbsp; &nbsp; RA<br>
          PUSH&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; PS</td>
      <td><br>
      </td>
    </tr>
    <tr>
      <td>RET</td>
      <td>Return from subroutine</td>
    </tr>
    <tr>
      <td>RETI</td>
      <td>Return from
    </tr>
    <tr>
      <td>ROL{.wt}
          &nbsp; RA, descriptor<br>
          ROR{.wt} &nbsp; RA, descriptor</td>
      <td>Rotate.<br>
        See notes on shift instructions below.</td>
    </tr>
    <tr>
      <td>ROXL{.wt}&nbsp;RA, descriptor<br>
          ROXR{.wt}&nbsp; RA, descriptor</td>
      <td>Rotate extended with X bit.<br>
        See notes on shift instructions below.</td>
    </tr>
    <tr>
      <td>SQRT</td>
      <td>This calculates the square root of R1.<br>
        The result, rounded down, is put into R0. R1 holds the
        remainder. R2 is unchanged. R3 will be set to zero.<br>
      </td>
    </tr>
    <tr>
      <td>ST.sz&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; address, RA<br>
          ST.sz&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (RI), RC<br>
          ST.sz&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (RI++), RC<br>
          ST.sz&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (SP + m), RA</td>
      <td>The m value used for stack relative addressing is 8 bit
        unsigned. </td>
    </tr>
    <tr>
      <td>SUB&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RA, RB</td>
      <td>RB may not equal RA</td>
    </tr>
    <tr>
      <td>SUBX&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R0, R1</td>
      <td><br>
      </td>
    </tr>
    <tr>
      <td>SXT&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RA</td>
      <td>Sign extend LS byte of register to fill the register</td>
    </tr>
    <tr>
      <td>TEST&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RA</td>
      <td>Set status bits Z, N according to register</td>
    </tr>
    <tr>
      <td>TRAP</td>
      <td>Pushes PS and return address and then takes vector #3.</td>
    </tr>
    <tr>
      <td>XOR&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; RA, RB</td>
      <td>RB may equal RA</td>
    </tr>
  </tbody>
</table>

<h3>Bit Instruction Descriptors:</h3>
<p>The descriptor specifies the target bit and may be either a 4 bit
  immediate value or a general purpose register (R0..R3). If a
  register is specified then only the least significant 4 bits are
  used. For example:</p>
  <p>
  BSET&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R0, #3<br>
  BCLR&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &nbsp; R1, R2
</p>
<h3>Shift Instruction Descriptors:</h3>
<p>The descriptor specifiers the shift to apply and is a 15 bit
  signed value ranging -16..15. It may be either a 5 bit signed
  immediate value or a general purpose register (R0..R3). If a
  register is specified then only the least significant 5 bits are
  used. For example:
</p>
<p>LSL&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R0, #3<br>
    ASR&nbsp; &nbsp;&nbsp;&nbsp;&nbsp; &nbsp; R1, R2<br>
</p>
<p>If the descriptor is a register then the instruction may be
  qualified with ".wt" in which case a weight value is calculated.
  The shift is executed as specified and the number of times a 1
  valued bit is shifted out of the least significant register
  position is counted. At the end of the shift operation this count
  is stored in the destination register rather than the result of
  the shift. For example:
</p>
<p>
  ASR.wt&nbsp;&nbsp;&nbsp;&nbsp; R1, R2<br>
</p>